Question 5 of 7: Analog-to-Digital Conversion

Question 5: Analog-to-Digital Conversion (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

a) A successive-approximation (SAR) converter performs a binary search: it sets the most significant bit of an internal register to 1 (all others 0), drives that code through a DAC, and a comparator checks whether the DAC output is above or below the held input. If the DAC output is too high, that bit is cleared back to 0; otherwise it is kept. The converter then moves to the next bit down and repeats the same trial-and-compare step, working one bit at a time from MSB to LSB, so an $N$-bit conversion completes in exactly $N$ comparison cycles.

b) A SAR conversion takes $N$ clock cycles to resolve $N$ bits, during which every bit decision compares against the same analog value. If the input were allowed to keep moving during that window, each bit's comparison would be testing against a different, shifting target, and the resulting code would not correspond to any single, valid sample of the input. A sample-and-hold circuit freezes the analog value for the full conversion window so that all $N$ bit decisions are made against one consistent, unchanging voltage.

c) Given. ADC conversion (sampling) rate $f_s=5000$ conversions/second.

Find. The maximum input frequency that can be correctly (unambiguously) sampled.

Approach. Apply the Nyquist sampling criterion, $f_{max}=f_s/2$.

1. Nyquist limit. $$f_{max}=\dfrac{f_s}{2}=\dfrac{5000\ \text{Hz}}{2}=\boxed{2500\ \text{Hz}}.$$

If the input contains energy above $2500\ \text{Hz}$, that content is under-sampled: each high-frequency cycle is captured at less than two samples per period, so the digitized data cannot reconstruct it. The under-sampled energy does not simply disappear — it folds back (aliases) into the correctly-sampled band, appearing as a spurious lower-frequency component at $|f_{in}-n f_s|$ that is mathematically indistinguishable from a genuine signal at that alias frequency.

d) A low-pass anti-aliasing filter must be placed ahead of the converter (the question says "ahead of the digital to analog converter," which is almost certainly a misprint for "analog to digital converter" — the whole question concerns the ADC's own sampling limit, and an anti-aliasing filter is meaningless in front of a DAC, so it is answered here as the ADC's own input filter). Its required specification is a cutoff frequency at or below the Nyquist frequency found in part (c), $2500\ \text{Hz}$, with enough stopband attenuation and rolloff (filter order) that any input energy above that cutoff is suppressed below the converter's own quantization noise floor before it reaches the sampler — a gentle single-pole filter set exactly at $2500\ \text{Hz}$ still passes significant energy well above it and is normally not steep enough on its own.

e) Given. 12-bit ADC accepting a $\pm5\,\text{V}$ input range (full-scale span $10\,\text{V}$); the actual input signal only spans $\pm1\,\text{V}$ (a $2\,\text{V}$ span).

Find. The ADC's resolution in volts, and how it can be improved for this signal.

Approach. Divide the full-scale span by the number of codes for the native resolution, then compare the signal's own span to the full range to see how much of the converter's dynamic range the signal actually uses.

1. Native resolution (one LSB). A 12-bit converter has $2^{12}=4096$ codes across its full $10\,\text{V}$ span: $$\text{LSB}=\dfrac{10\ \text{V}}{4096}=\boxed{2.441\ \text{mV}}.$$
2. How much of the range the signal uses. The $\pm1\,\text{V}$ ($2\,\text{V}$) signal occupies only $$\dfrac{2\ \text{V}}{10\ \text{V}}=20\%$$ of the converter's full span, i.e. only about $4096\times0.20\approx819$ of the 4096 codes ever get exercised — the remaining 80% of the converter's dynamic range is wasted on voltages the signal never reaches.
3. Improving it: pre-amplify to fill the range. Inserting a fixed-gain amplifier ahead of the ADC that scales the $\pm1\,\text{V}$ signal up to fill the full $\pm5\,\text{V}$ input span requires a gain of $$G=\dfrac{5\ \text{V}}{1\ \text{V}}=5,$$ after which every one of the 4096 codes is spread across the original $2\,\text{V}$ signal span instead of the full $10\,\text{V}$, giving an effective resolution (referred back to the original signal) of $$\boxed{\text{LSB}_{eff}=\dfrac{2.441\ \text{mV}}{5}\approx0.4883\ \text{mV}}$$ — a five-fold improvement, at the cost of needing a well-characterized, low-noise/low-drift gain stage ahead of the converter.