Question 6 of 7: Full-Wave Bridge Rectifier Design
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
04-BS-4 — Electric Circuits and Power — National Exam, May 2014.
Closed book; one aid sheet permitted; Casio/Sharp approved calculator only.
Any five of the seven questions constitute a complete paper — every question is answered.
Reference texts: Sadiku & Alexander, Fundamentals of
Electric Circuits (DC/AC network analysis, Thevenin, resonance);
Chapman, Electric Machinery Fundamentals (magnetic circuits);
Boylestad, Electronic Devices and Circuit Theory (diode rectifiers);
Mano, Digital Design (combinational logic).
Find. The rectifier topology and conduction pattern; peak
input/output voltages; the qualitative output shape with the RC-loaded filter cap; and
an RC low-pass design meeting the 20 dB spec.
Full-wave bridge rectifier: D1–D4 diamond bridge, resistive
load $R_L$ in parallel with a smoothing capacitor $C$.
Approach. A full-wave bridge always routes current through TWO
diodes in series (never one), so every conduction path costs $2V_D$ of offset; find
the raw peak, subtract the two-diode drop, then treat the capacitor-loaded output as an
exponential decay between successive 120 Hz peaks (full-wave ripple frequency is
twice the line frequency), and finally size an RC low-pass to the stated dB spec.
(a) Topology and conduction. During the positive AC half-cycle,
current flows source(+)→D1→$R_L$→D3→source(−) (D1, D3
conduct; D2, D4 reverse-biased/off). During the negative half-cycle, current flows
source(− side now high)→D2→$R_L$→D4→source (D2, D4 conduct;
D1, D3 off). Either pair always delivers current the SAME direction through $R_L$,
which is the defining feature of full-wave rectification. Peak input:
$$V_{pk}=\sqrt2\,V_{rms}=\sqrt2(12)=16.97\text{ V}$$
Two diodes always conduct in series, so the output peak loses $2V_D$:
$$\boxed{V_{out,pk}=V_{pk}-2V_D=16.97-1.2=15.77\text{ V}}$$
The output is a train of half-sine "humps" at twice the input frequency (120 Hz),
each hump the rectified magnitude of the input, flattened at the top by the two-diode
offset.
(b) Output with $R_L=1000\,\Omega\parallel C=8\,\mu\text{F}$.
Between successive peaks the capacitor discharges through $R_L$ with time constant
$$\tau=R_LC=(1000)(8\times10^{-6})=8.0\text{ ms}$$
The peaks recur every $T=1/(2\times60)=8.33$ ms (full-wave ripple period), so
$\tau\approx T$ — NOT a well-filtered case; the cap discharges a substantial
fraction before the next peak recharges it:
$$V_{ripple}=V_{out,pk}\left(1-e^{-T/\tau}\right)
=15.77\left(1-e^{-8.33/8.0}\right)$$
$$\boxed{V_{ripple}\approx10.2\text{ V (peak-to-peak)}}$$
so the sketch shows the output charging to 15.77 V at each hump peak, then decaying
exponentially down to about 5.6 V just before the next diode pair turns back on
— a visibly saw-toothed, incompletely-filtered DC with roughly 65% ripple, not a
smooth flat line.
(c) RC low-pass filter, −20 dB at 120 Hz. For a first-order
RC low-pass, $|H(j\omega)|=1/\sqrt{1+(\omega R_fC_f)^2}$ relative to unity DC gain.
$-20$ dB means $|H|=0.1$:
$$\sqrt{1+(\omega R_fC_f)^2}=10 \;\Rightarrow\; \omega R_fC_f=\sqrt{99}=9.950$$
Choosing a practical $R_f=2\,\text{k}\Omega$ (a free design choice; only the dB
spec is given):
$$C_f=\dfrac{9.950}{2\pi(120)(2000)}
\;\Rightarrow\;\boxed{C_f=6.60\,\mu\text{F}}$$
giving a corner frequency $f_c=1/(2\pi R_fC_f)=12.06$ Hz, comfortably below the
120 Hz ripple to be rejected. Check:
$20\log_{10}\!\big(1/\sqrt{1+(2\pi\cdot120\cdot R_fC_f)^2}\big)=-20.00$ dB
✓.
