NivaarExam PrepOfficial exam papers ↗

04-BS-4 · May 2018

Question 6 of 7: Full-Wave Bridge Rectifier Design

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

04-BS-4 Electric Circuits and Power — May 2018
National Exams, 3 hours, closed book (one aid sheet permitted). Any five of the seven questions constitute a complete paper; all seven are solved below as a complete study resource.

Reference texts

Question 6: Full-Wave Bridge Rectifier Design (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Ideal AC source: $60$ Hz, $20$ VRMS, feeding a $50$ kΩ resistive load through a rectifier.

Given data
$V_{s,\text{rms}}$$f$$R_{LOAD}$
20 V60 Hz50 kΩ

Find. Number of diodes and schematic; sketches of input/output voltage/current and diode currents; peak and average load current; and the effect of a $0.5$ V diode drop on the waveforms.

20V_rms, 60Hz+D1D2D3D4R_LOAD+ v_out -
Figure 6: Full-wave bridge rectifier -- 20 Vrms, 60 Hz, into 50 kΩ

Approach. A full-wave bridge rectifier (the question explicitly asks about all "four" diodes, which only a bridge topology has) conducts diagonal diode pairs on alternate half-cycles, so the load sees both half-cycles of the input as positive pulses; peak/average current follow directly from the rectified peak voltage.

  1. a) Diode count and topology. A full-wave bridge rectifier needs $\boxed{4\text{ diodes}}$ arranged in a diamond: $D_1,D_3$ conduct (source $+$ half-cycle) delivering current one way through $R_{LOAD}$, while $D_2,D_4$ conduct on the opposite half-cycle, delivering current through $R_{LOAD}$ in the same direction — see the schematic above.
  2. b) Waveform sketches (ideal diodes). $v_{in}(t)=20\sqrt2\cos(2\pi\cdot60\,t)$ V is a plain sinusoid. $v_{out}(t)=|v_{in}(t)|$ is the full-wave-rectified sinusoid (every half-cycle is a positive "hump," period $8.33$ ms $=T/2$ where $T=1/60$ s). $i_{out}(t)=v_{out}(t)/R_{LOAD}$ has the identical shape, scaled by $1/50\text{k}\Omega$. Each diode carries current only during its conducting half-cycle: $D_1,D_3$ carry the full $i_{out}(t)$ waveform during the positive input half-cycle and zero otherwise; $D_2,D_4$ carry it during the negative input half-cycle and zero otherwise — i.e. each diode's current is exactly every other hump of $i_{out}(t)$, and together the two pairs reconstruct the continuous full-wave output.
  3. c) Peak and average load current (ideal diodes). $$V_{pk}=V_{s,\text{rms}}\sqrt2=20\sqrt2=28.28\text{ V}\ ,\qquad I_{pk}=\frac{V_{pk}}{R_{LOAD}}=\frac{28.28}{50\,000}=\boxed{0.5657\text{ mA}}$$ $$I_{avg}=\frac{2I_{pk}}{\pi}=\frac{2(0.5657\text{ mA})}{\pi}=\boxed{0.3601\text{ mA}}$$
  4. d) Effect of a $0.5$ V diode on-state drop. At every instant, current passes through two diodes in series (e.g. $D_1$ and $D_3$), so the output is reduced by $2(0.5\text{ V})=1.0$ V relative to $|v_{in}(t)|$ whenever conduction occurs, and $v_{out}(t)=0$ whenever $|v_{in}(t)|\lt1.0$ V (both diodes cut off near each zero-crossing, producing a brief flat "dead zone" the ideal-diode sketch in (b) does not have). $$v_{out,pk}=V_{pk}-2(0.5\text{ V})=28.28-1.0=\boxed{27.28\text{ V}}$$
Final results — Question 6
QuantityValue
Diode count4 (full bridge)
$V_{pk}$ (input)28.28 V
$I_{pk}$ (ideal diodes)0.5657 mA
$I_{avg}$ (ideal diodes)0.3601 mA
$v_{out,pk}$ (0.5 V drop)27.28 V
Check: with real diodes the output current's peak and average also shrink in proportion to $v_{out,pk}/V_{pk}$ ($I_{pk}=0.5457$ mA, $I_{avg}=0.3474$ mA) and a short dead-zone appears near each zero crossing; this is a standard non-ideal correction, not an error in the ideal-diode analysis of part (c).