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04-BS-8: May 2018

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Boolean Expression Evaluation and a Dual Crossbar-Switch Network
  2. Question 2 FPGA Architecture, and a 2’s-Complement→Sign-Magnitude Converter
  3. Question 3 Sequence-Detector FSM — “1100” After ≥3 Zeros
  4. Question 4 T Flip-Flop from a JK, and a 2-Bit Shift-Register State Detector
  5. Question 5 Barrel Shifter — Concept and a 4:1-MUX Realization

Start with Question 1 →

04-BS-8 Digital Logic Circuits — May 2018
National Exams, 3 hours, closed book (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet, both sides, permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, K-maps, PAL/PLA/FPGA architectures, flip-flop conversion, sequential-circuit design, arithmetic circuits; Floyd, Digital Fundamentals (11th ed., Pearson) — logic gates, multiplexers, shift registers, flip-flop characteristic tables.