T Flip-Flop from a JK, and a 2-Bit Shift-Register State Detector: 04-BS-8, May 2018, Q4

Question 4: T Flip-Flop from a JK, and a 2-Bit Shift-Register State Detector (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

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Part (b)(iii) does not specify an explicit $A$ sequence to waveform — only the clock frequency, reset condition and delays are given. The design below assumes the illustrative sequence $A=1,0,0,1,0$ applied before the five successive rising edges, chosen only to exercise every transition of $W$ (rise, hold, fall, hold, rise); the timing relationships shown (10 ns after each edge for $Q_1,Q_2$, a further 5 ns for $W$) hold identically for any other input sequence, since they follow purely from the stated propagation delays.

Given. Two positive-edge D flip-flops sharing one clock: $D_1=A$ (DFF1), $D_2=Q_1$ (DFF2) — i.e. a 2-bit serial shift register. $W=\overline{Q_1'\cdot Q_2'}$ (2-input NAND on the complemented outputs). Both flip-flops reset to $Q_1=Q_2=0$. 10 MHz clock (100 ns period); flip-flop propagation delay 10 ns; NAND propagation delay 5 ns.

Find. (a) A T-FF built from a JK-FF. (b)(i) synchronous or not, with justification; (ii) the state that $W$ detects; (iii) the $Q_1,Q_2,W$ waveforms.

Approach. (a) Compare the T-FF and JK-FF characteristic tables directly. (b)(i) check whether every flip-flop shares one clock edge with no combinational logic in the clock path. (ii) apply De Morgan to $W$ to read off which $(Q_1,Q_2)$ combination drives it low. (iii) simulate the shift-register + gate chain with the stated delays for an illustrative $A$ sequence.

Part (a) — T flip-flop from a JK flip-flop. The JK characteristic table is $Q^+=J\bar Q+\overline{K}Q$; the T (toggle) characteristic table is $Q^+=T\oplus Q = T\bar Q + \bar T Q$. Comparing term by term, tying $J=K=T$ makes $Q^+=T\bar Q+\bar T Q$ exactly — i.e. no additional gates are needed at all: wiring the single input $T$ directly to both the $J$ and $K$ pins of the JK flip-flop reproduces the toggle behaviour exactly (: $T=0\Rightarrow$ hold, $T=1\Rightarrow$ toggle). This is the standard, minimum (zero-gate) T-from-JK conversion.
Part (b)(i) — synchronous or asynchronous? Yes, synchronous. Both DFF1 and DFF2 are triggered by the identical CLK signal (no flip-flop’s clock is derived from another flip-flop’s output, which is the hallmark of an asynchronous/ripple design) and all state changes occur only at that one shared active clock edge; the NAND gate is purely combinational and sits outside the clock path (it only shapes the output $W$, it never feeds a clock input). Both criteria for a synchronous sequential circuit are satisfied.
Part (b)(ii) — state detected by the NAND gate. By De Morgan, $$W = \overline{Q_1'\cdot Q_2'} = Q_1+Q_2$$ so $W=0$ if and only if $Q_1'=Q_2'=1$, i.e. $Q_1=Q_2=0$. The gate is an active-low detector of the all-zero state $(Q_1,Q_2)=(0,0)$ — exactly the flip-flops’ own reset state; $W$ pulses low every time the 2-bit shift register returns to 00 and is high ($=1$) for every other state.
Part (b)(iii) — waveforms. With the illustrative sequence $A=1,0,0,1,0$ applied before the rising edges at $t=100,200,300,400,500$ ns: DFF1 always captures the current $A$; DFF2 always captures the previous $Q_1$ (one-cycle-delayed shift). Each flip-flop output changes 10 ns after its clock edge; $W$ recomputes 5 ns after whichever of $Q_1,Q_2$ last changed, i.e. 15 ns after the triggering edge. Simulated cycle-by-cycle: $Q_1$ rises at 110 ns ($W$ recomputes at 115 ns and rises, since the reset state 00 is left); at 210 ns $Q_1$ falls to 0 while $Q_2$ rises to 1 simultaneously ($W$ recomputes at 215 ns and stays high — still not the 00 state, just a different non-00 state); at 310 ns $Q_2$ falls to 0 while $Q_1$ is already 0, so the pair returns to 00 ($W$ falls at 315 ns); at 410 ns $Q_1$ rises again while $Q_2$ stays 0 ($W$ rises at 415 ns).
[Figure not reproduced: Fig. Q4(b) — the given circuit redrawn: 2-bit serial shift register (DFF1→DFF2) with a NAND(Q1′,Q2′)=W state-00 detector. See the official exam paper.]
Fig. Q4(b)(iii) — CLK, A, Q1, Q2, W for the illustrative sequence A=1,0,0,1,0 (10 MHz clock, 10 ns FF delay, 5 ns NAND delay).

Final results — Question 4
Item	Result
(a) T-FF from JK	$J=K=T$, zero extra gates
(b)(i)	Synchronous (one shared clock, no derived clocks)
(b)(ii)	$W$ active-low detects $(Q_1,Q_2)=(0,0)$
(b)(iii)	Each $Q_i$ changes 10 ns after its clock edge; $W$ changes 15 ns after the edge

Concept & Theory

Topic: Flip-flop conversion via characteristic-table matching; synchronous shift-register state detection; propagation-delay timing analysis.

Key relations: JK characteristic $Q^+=J\bar Q+\bar K Q$; T characteristic $Q^+=T\oplus Q$; De Morgan $\overline{x'y'}=x+y$; total delay from a triggering clock edge to a downstream gate output = flip-flop $t_{pd}$ + gate $t_{pd}$ (delays add along the signal path, they do not run in parallel).

Why this works: Setting $J=K=T$ collapses the JK table's four rows exactly onto the T table's two rows because $J=1,K=0$ (set) and $J=0,K=1$ (reset) never occur when $J=K$; only hold ($J=K=0$) and toggle ($J=K=1$) survive, which is precisely what a T flip-flop does. For the timing, because DFF2's D input is DFF1's Q output (not a fresh copy of A), $Q_2$ always lags $Q_1$ by exactly one clock period — a defining property of a shift register.

Common pitfall: Assuming $W$ pulses HIGH to indicate a detected state; since it is built from a NAND (not a NOR or AND-then-invert-elsewhere), the detected state drives $W$ LOW, and $W$ idles HIGH everywhere else — the opposite polarity of a more familiar AND-based "match" indicator.

Source: Mano & Ciletti, Digital Design §6 (flip-flop characteristic tables and conversion, shift registers); Floyd, Digital Fundamentals §on propagation delay and timing diagrams.

Question 4 of 5: T Flip-Flop from a JK, and a 2-Bit Shift-Register State Detector

Question 4: T Flip-Flop from a JK, and a 2-Bit Shift-Register State Detector (25 marks)