Question 1 of 6: Digital Design and VHDL Concepts

Question 1: Digital Design and VHDL Concepts (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Find. The single best answer, with reasoning, for each of the ten 2-mark sub-questions on VHDL/digital-design terminology.

1.1 — Answer: C. RTL stands for Register Transfer Level — a design abstraction that describes a circuit as data moving between registers through combinational logic, one clock transfer at a time. "Relational Timing Logic" (A) and "Relative Transfer Latches" (B) are invented distractors with no standard meaning.

1.2 — Answer: B. XOR is the "difference detector": $A\oplus B=1$ iff $A\ne B$. Its truth table is $0\oplus0=0,\ 0\oplus1=1,\ 1\oplus0=1,\ 1\oplus1=0$ — true precisely when the two inputs differ, so B is correct (A describes XNOR; C describes OR).

1.3 — Answer: C. Within an architecture body, a process is placed alongside concurrent signal assignments and component instantiations — it is itself one of the concurrent statements, evaluated whenever an event occurs on a signal in its sensitivity list. The statements written INSIDE a process (variable assignment, if/case, loop) are sequential; the process construct as a whole is not.

1.4 — Answer: C. "Sequential" is the direct opposite of "concurrent": happening in steps, one after the other, exactly how statements inside a VHDL process execute (top to bottom, in program order). (A) confuses it with speed; (B) describes repetition, not order.

1.5 — Answer: B. Syntax is a language's legal structure/grammar (how statements may be written); semantics is what those statements mean (their effect). Together they refer to grammar and meaning. (A) restates syntax alone under a different name; (C) is unrelated.

1.6 — Answer: B. Propagation delay $t_{pd}$ is the real, physical delay through combinational logic or a gate: the time between an input changing and the corresponding output settling to its new value. It is unrelated to flip-flop initialization (A) and is not the clock period (C, which is instead bounded below by the sum of propagation delays around the slowest path).

1.7 — Answer: B. A process's sensitivity list names the signals whose events re-trigger it — for a combinational process this must be every signal the process READS, i.e. process inputs. Including outputs (C) is unnecessary (an output only changes as a RESULT of the process running, so listing it as a trigger risks an artificial or incorrect re-evaluation) and would not match standard practice.

1.8 — Answer: A. Concurrent statements do not execute "in the order written" (that is the defining property of sequential code, B) — each concurrent statement instead executes whenever an event occurs on a signal it depends on ("executing when triggered"), independent of its textual position in the architecture. (C) mistakes an ordinary event-driven trigger for a fixed timed delay.

1.9 — Answer: C. All three of signal assignment, loop, and variable assignment are sequential statements, valid only inside a process/subprogram. (A) and (B) each smuggle in a concurrent construct ("selected concurrent signal assignment" and "conditional concurrent signal assignment" respectively), so they are not lists of three purely sequential statements.

1.10 — Answer: A. A VHDL variable is updated instantly when its assignment statement executes, unlike a signal (which only takes its new value after a delta-cycle/simulation-delay). This immediate-update semantics is exactly what lets a variable be read back later in the same process invocation and see the value just assigned.