Question 6 of 6: Memory Chip Capacity, Composition, and Bus Interfacing

Question 6: Memory Chip Capacity, Composition, and Bus Interfacing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) A single memory chip: 15 address lines A0–A14, R/W! direction control, E chip-enable (must be 1 to access; tri-states D3–D0 when 0), 4-bit bidirectional data D3–D0. (b) Build an 8-bit-wide, 64KB chip from copies of (a)'s chip plus a few gates. (c) A system bus with 32 address lines L0–L31, ME (access-in-progress), R/W!, and an 8-bit bidirectional D0–D7 bus; the array from (b) must respond only to addresses 0x10000–0x1FFFF.

Find. (a) the chip's capacity in bytes; (b) how many chips (and what glue logic) build the 8-bit×64KB array; (c) how to wire that array into the given 32-bit-address/8-bit-data system bus so it answers only the specified 64KB window.

Approach. (a) multiply the number of addressable locations by the data width; (b) widen the data bus by placing chips side-by-side, then deepen the address space by stacking width-pairs and using one extra address bit to enable only the matching depth-group; (c) split the 32-bit system address into the low bits the array itself consumes and the high bits that must be decoded against the fixed window prefix, gating the array's enable with that decode ANDed with ME.

1. Part (a) — single-chip capacity. 15 address lines address $$\text{locations}=2^{15}=32{,}768$$ distinct rows, each holding 4 bits (D3–D0): $$\text{capacity}=32{,}768\times4\ \text{bits}=131{,}072\ \text{bits}=\frac{131{,}072}{8}=\boxed{16{,}384\ \text{bytes}=16\text{KB}}.$$
2. Part (b) — building an 8-bit, 64KB array. Widen the bus: the target is 8 bits wide but each chip only supplies 4, so place TWO chips side by side, sharing the same address lines A0–A14 and the same enable — one chip drives D0–D3, the other D4–D7. That pair is a $32\text{K}\times8=32\text{KB}$ "row." Deepen the capacity: the target is 64KB $=2\times32\text{KB}$, so TWO such rows are needed, selected by one extra address bit, $A_{15}$, that is NOT available on any individual chip: $$\text{chips}=\underbrace{2}_{\text{width}}\times\underbrace{2}_{\text{depth}}=\boxed{4\ \text{chips}}.$$ Feed $A_0$–$A_{14}$ identically to all four chips. Build each row's enable from $A_{15}$ and an overall "array selected" signal $CS$ (supplied from part (c)) with one inverter and two AND gates: $$E_{row0}=CS\cdot\overline{A_{15}},\qquad E_{row1}=CS\cdot A_{15}.$$ Only the addressed row's two chips ever have $E=1$; the other row's D3–D0 stay high-Z, so the two rows can safely share the same D0–D3/D4–D7 bus lines without contention. $R/W\!\!\;\!$ is wired identically to all four chips.
3. Part (c) — connecting the 64KB array to the system bus. First confirm the requested window is exactly one array's worth: $\texttt{0x1FFFF}-\texttt{0x10000}+1=\texttt{0x10000}=65{,}536$ bytes $=64$KB, so a single non-aliased decode window suffices. The array itself only needs 16 address bits ($A_0$–$A_{14}$ plus the depth-select $A_{15}$ from part (b)); those come directly from the system bus's own low-order lines: $$A_0\text{–}A_{14}=L_0\text{–}L_{14},\qquad A_{15}=L_{15}.$$ The remaining high-order lines $L_{16}$–$L_{31}$ must all match the fixed prefix of 0x10000 (i.e. $L_{16}=1$ and every bit above it is 0) for the array to be selected: $$CS_{decode}=L_{16}\cdot\overline{L_{17}}\cdot\overline{L_{18}}\cdots\overline{L_{31}}.$$ The array is enabled only during an actual bus transaction, so gate the decode with ME to form the $CS$ used in part (b): $$CS=CS_{decode}\cdot ME.$$ $R/W\!\!\;\!$ passes straight through unchanged to every chip, and the system's $D_0$–$D_7$ bus connects directly (bidirectionally) to the array's combined data pins — already tri-stated correctly by the $E_{row0}/E_{row1}$ logic of part (b) whenever $CS=0$.