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25-Comp-A3 Computer Architecture: May 2014

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Instruction Set Extension, Memory Traffic, and I/O
  2. Question 2 Signed/Unsigned Arithmetic, Floating-Point Precision, and Array Addressing
  3. Question 3 Cache Organization and the Register/Cache Tradeoff
  4. Question 4 Pipelining, Parallel Execution Strategies, and Hardware Specialization
  5. Question 5 Multi-Cycle CPU Performance Comparison
  6. Question 6 Memory Chip Capacity, Composition, and Byte-Interleaved Bus Interfacing

Start with Question 1 →

98-Comp-A3, Computer Architecture — National Exams, May 2014 (paper header reads "December 2013"). Open-book, 3 hours; six questions of equal value (20 marks each); FIVE constitute a complete exam (all six answered below as a complete study resource).

Reference texts: Patterson & Hennessy, Computer Organization and Design, 6th ed. — instruction encoding & ISA compatibility, I/O (Q1), data representation & IEEE-754 floating point & array addressing (Q2), cache organization (Q3), pipelining & parallelism (Q4), CPU performance (Q5), and memory technology (Q6); Mano & Ciletti, Digital Design, 6th ed. — memory decoding and chip composition (Q6).