Question 6 of 6: Memory Chip Capacity, Composition, and Byte-Interleaved Bus Interfacing

Question 6: Memory Chip Capacity, Composition, and Byte-Interleaved Bus Interfacing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) A single memory chip: 24 address lines A0–A23, R/W̄ direction control, E chip-enable, 2-bit bidirectional data D1–D0 (high-Z when $E=0$). (b) Build an 8-bit-wide, 32MB chip from copies of (a)'s chip plus a few gates. (c) A system bus with 32 address lines L0–L31, ME (access-in-progress), R/W̄, and an 8-bit bidirectional D0–D7 bus; TWO of the 32MB composites from (b) must be byte-interleaved to answer a 64MB window starting at 0x10000000.

Find. (a) the chip's capacity in bytes. (b) how many chips (and what glue logic) build the 8-bit×32MB composite. (c) how to byte-interleave two such composites into the given 32-bit-address/8-bit-data system bus so together they answer exactly the specified 64MB window.

Approach. (a) multiply addressable locations by data width. (b) widen the data bus by placing chips side-by-side, then deepen the address space by stacking width-pairs and using one extra address bit to enable only the matching depth-group. (c) split the 32-bit system address into the low bit that alternates which composite is selected (byte interleave), the next bits that feed each composite's own address pins directly, and the high, fixed bits that must be decoded against the window's base address.

1. Part (a) — single-chip capacity. 24 address lines address $$\text{locations}=2^{24}=16{,}777{,}216$$ distinct rows, each holding 2 bits (D1–D0): $$\text{capacity}=16{,}777{,}216\times2\ \text{bits}=33{,}554{,}432\ \text{bits}=\frac{33{,}554{,}432}{8}=\boxed{4{,}194{,}304\ \text{bytes}=4\text{MB}}.$$
2. Part (b) — building an 8-bit, 32MB composite. Widen the bus: the target is 8 bits wide but each chip only supplies 2, so place FOUR chips side by side, sharing the same address lines A0–A23 and the same enable — chip 0 drives D0–D1, chip 1 drives D2–D3, chip 2 drives D4–D5, chip 3 drives D6–D7. That group of 4 is one $16\text{M}\times8=16\text{MB}$ "row." Deepen the capacity: the target is 32MB $=2\times16\text{MB}$, so TWO such rows are needed, selected by one extra address bit $A_{24}$ not available on any individual chip: $$\text{chips}=\underbrace{4}_{\text{width}}\times\underbrace{2}_{\text{depth}}=\boxed{8\ \text{chips}}.$$ Feed $A_0$–$A_{23}$ identically to all eight chips. Build each row's enable from $A_{24}$ and an overall "array selected" signal $CS$ (supplied from part (c)) with one inverter and two AND gates: $$E_{row0}=CS\cdot\overline{A_{24}},\qquad E_{row1}=CS\cdot A_{24}.$$ Only the addressed row's four chips ever have $E=1$; the other row's D1–D0 pins stay high-Z, so both rows can safely share the same D0–D7 bus lines without contention. $R/W\!\!\;\!\!\;\overline{\phantom{x}}$ is wired identically to all eight chips. This composite has $24+1=25$ address lines total, matching $2^{25}=33{,}554{,}432=32\text{MB}$.
3. Part (c) — byte-interleaving two 32MB composites onto the system bus. First confirm the requested window is exactly TWO composites' worth: from $\texttt{0x10000000}$, a $64\text{MB}=2^{26}$-byte window spans $\texttt{0x10000000}$–$\texttt{0x13FFFFFF}$, and $64\text{MB}=2\times32\text{MB}$ — matching the two composites available.
   Because addressing is BYTE-interleaved (even bytes → composite 0, odd bytes → composite 1), the system address's LOWEST bit $L_0$ selects which composite answers, and it is NOT fed to either composite's own address pins — each composite instead receives the address of the BYTE-PAIR it is inside, i.e. bits $L_1$ through $L_{25}$ (25 bits, exactly matching each composite's own 25 address lines from part (b)): $$A_0\text{–}A_{24}\ (\text{composite})=L_1\text{–}L_{25}\ (\text{system}).$$ The remaining high-order lines $L_{26}$–$L_{31}$ must match the fixed prefix of the 64MB window's base address 0x10000000: since $\texttt{0x10000000}=2^{28}$, right-shifting by the 26 bits the window itself consumes gives $2^{28}/2^{26}=4=\texttt{0b000100}$, so $$CS_{decode}=\overline{L_{26}}\cdot\overline{L_{27}}\cdot L_{28}\cdot\overline{L_{29}}\cdot\overline{L_{30}}\cdot\overline{L_{31}}.$$ Gate the decode with ME (an access is actually happening) to obtain the $CS$ used in part (b), and further split by parity to select which composite is enabled: $$CS=CS_{decode}\cdot ME,\qquad CS_{even}=CS\cdot\overline{L_0}\ (\text{composite 0}),\qquad CS_{odd}=CS\cdot L_0\ (\text{composite 1}).$$ $R/W\!\!\;\!\!\;\overline{\phantom{x}}$ passes straight through unchanged to both composites, and the system's $D_0$–$D_7$ bus connects directly (bidirectionally) to whichever composite's own D0–D7 is enabled — the two composites never drive the bus simultaneously because $CS_{even}$ and $CS_{odd}$ are mutually exclusive (they differ only in $L_0$).