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25-Comp-A3 Computer Architecture: December 2015

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Cache Size, Control-Unit Style, and Bus-Width Performance
  2. Question 2 Cache Replacement, I/O Techniques, and RISC Design
  3. Question 3 Cache Write Consistency, Instruction Encoding, and Multiplication Hardware
  4. Question 4 DRAM vs. SRAM, IEEE-754 Decoding, and Instruction-Encoding Sizing
  5. Question 5 Hit-Rate Sizing, Infix-to-RPN, and Control-Unit Design
  6. Question 6 Unified Memory, Addressing Modes, and Micro-Operation Sequences

Start with Question 1 →

98-Comp-A3, Computer Architecture — National Exams, December 2015. Closed-book, 3 hours; six questions of equal value (20 marks each); FIVE constitute a complete exam (all six answered below as a complete study resource).

Reference texts: Patterson & Hennessy, Computer Organization and Design, 6th ed. — memory hierarchy & cache performance (Q1a, Q2a, Q3a, Q5a), instruction encoding & RISC design (Q2c, Q3b, Q4c), IEEE-754 floating point (Q4b), and memory technology (Q4a); Mano & Ciletti, Digital Design, 6th ed. — control-unit design, register-transfer micro-operations, stack/RPN notation, and binary-multiplication hardware (Q1b, Q3c, Q5b–d, Q6a–c).