Question 4 of 6: DRAM vs. SRAM, IEEE-754 Decoding, and Instruction-Encoding Sizing

Question 4: DRAM vs. SRAM, IEEE-754 Decoding, and Instruction-Encoding Sizing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) The two common RAM technologies. (b) Two 32-bit IEEE-754 single-precision bit patterns (1 sign + 8 exponent + 23 mantissa, bias 127). (c) 48 registers, 191 opcodes, 16-bit immediates, and an instruction mix of 20%/30%/25%/25% across four operand shapes, with every instruction padded to a whole number of bytes.

Find. (a) The structural/performance/cost differences between DRAM and SRAM. (b) The decimal value each bit pattern encodes. (c) The byte-rounded bit-width of each instruction type, and the % memory saved by variable- vs. fixed-length encoding.

Approach. (a) compare storage cell design, refresh requirement, speed, density and cost. (b) apply $(-1)^S\times1.M\times2^{E-127}$ directly to each pattern. (c) size the register and opcode fields from the counts given ($\lceil\log_2 n\rceil$), build each instruction type's raw bit total, round each up to the next multiple of 8, then compare the mix-weighted average against the fixed (worst-case) length.

1. Part (a) — DRAM vs. SRAM. SRAM stores each bit in a bistable flip-flop (typically 6 transistors), holding its value as long as power is applied — no refresh is needed. It is much faster (single-digit-ns access) because reading doesn't destroy the stored charge, but each cell is large, so SRAM has low density and is expensive per bit; it is used for caches and register files, where speed dominates. DRAM stores each bit as charge on a single capacitor (1 transistor + 1 capacitor per cell), which leaks over time and MUST be periodically refreshed (read and rewritten) every few milliseconds or the data is lost. It is slower (tens of ns, plus refresh overhead competes for the same access circuitry) but far denser and cheaper per bit, so it is used for main memory, where capacity per dollar dominates. SRAM: fast, no refresh, low density, expensive — caches/registers. DRAM: slower, needs refresh, high density, cheap — main memory.
2. Part (b) — IEEE-754 decoding. Applying $(-1)^S\times(1+\sum m_i 2^{-i})\times2^{E-127}$ to each pattern (the paper labels the two patterns (3) and (4), continuing the numbering of its own sub-item list):
   (3) $S=1$, $E=10000011_2=131$, $M=11000000\ldots_2$: mantissa fraction $=2^{-1}+2^{-2}=0.5+0.25=0.75$, so significand $=1.75$; exponent $=131-127=4$. $$(-1)^1\times1.75\times2^4=-1.75\times16=\boxed{-28}$$ (4) $S=0$, $E=10000000_2=128$, $M=0$: significand $=1.0$; exponent $=128-127=1$. $$(+1)\times1.0\times2^1=\boxed{2.0}$$
3. Part (c1) — per-type instruction bit-width. The register field must distinguish 48 registers: $\lceil\log_2 48\rceil=6$ bits ($2^6=64\ge48$). The opcode must distinguish 191 instructions: $\lceil\log_2 191\rceil=8$ bits ($2^7=128<191\le256=2^8$). Immediates are given directly as 16 bits. Each instruction is opcode + its operand fields, rounded UP to the next multiple of 8 bits:

   Type (fraction)	Fields	Raw bits	Rounded to bytes
   1 in-reg, 1 out-reg (20%)	$8+6+6$	20 bits	$\lceil20/8\rceil\times8=\boxed{24\ \text{bits (3 B)}}$
   2 in-reg, 1 out-reg (30%)	$8+6+6+6$	26 bits	$\lceil26/8\rceil\times8=\boxed{32\ \text{bits (4 B)}}$
   1 in-reg, 1 out-reg, 1 imm (25%)	$8+6+6+16$	36 bits	$\lceil36/8\rceil\times8=\boxed{40\ \text{bits (5 B)}}$
   1 imm, 1 out-reg (25%)	$8+6+16$	30 bits	$\lceil30/8\rceil\times8=\boxed{32\ \text{bits (4 B)}}$

4. Part (c2) — fixed vs. variable-length memory. A fixed-length encoding must be wide enough to hold the LARGEST instruction type (the 36-bit, 1-in/1-out/1-imm type), rounded to a byte multiple: $$L_{fixed}=\lceil36/8\rceil\times8=\boxed{40\ \text{bits}=5\ \text{bytes, for every instruction}}.$$ A variable-length encoding lets each type use only its own rounded width, so the average bytes/instruction is the mix-weighted sum of the byte-rounded widths from the table above: $$\bar L_{var}=0.20(3)+0.30(4)+0.25(5)+0.25(4)=0.6+1.2+1.25+1.0=\boxed{4.05\ \text{bytes/instruction}}.$$ The memory saved, as a fraction of the fixed-length program size, is $$\frac{L_{fixed}-\bar L_{var}}{L_{fixed}}=\frac{5-4.05}{5}=\frac{0.95}{5}=\boxed{0.19=19\%\ \text{less memory}}$$ using variable-length encoding compared to fixed-length.