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25-Comp-A3 Computer Architecture: May 2016

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Cache Organization, Control-Unit Signals, and Bus-Width Transfer Rate
  2. Question 2 Cache Block Size, I/O Drawbacks, and Parallelism
  3. Question 3 Cache Write Policy, Instruction Encoding Length, and Binary Division Hardware
  4. Question 4 Memory Volatility, IEEE-754 Decoding, and Variable-Length Encoding Savings
  5. Question 5 Memory-Hierarchy Access Time, RPN-to-Infix, and Control-Unit Styles
  6. Question 6 Branch Prediction, Addressing Modes, Shift Types, and Non-Volatile Memory Families

Start with Question 1 →

98-Comp-A3, Computer Architecture — National Exams, May 2016. Closed-book, 3 hours; six questions of equal value (20 marks each); FIVE constitute a complete exam (all six answered below as a complete study resource).

Reference texts: Patterson & Hennessy, Computer Organization and Design, 6th ed. — memory hierarchy & cache design (Q1a, Q2a, Q3a, Q5a), bus/data-transfer performance (Q1c), instruction-level parallelism (Q2c), instruction encoding & RISC/CISC tradeoffs (Q3b, Q4c), IEEE-754 floating point and memory technology (Q4a–b), branch prediction and addressing modes (Q6a–b); Mano & Ciletti, Digital Design, 6th ed. — control-unit design (Q1b, Q5c–d), unsigned binary division hardware (Q3c), reverse-Polish/stack notation (Q5b), and shift operations (Q6c); Stallings, Data and Computer Communications — programmed vs. interrupt-driven I/O (Q2b).