Question 4 of 6: Memory Volatility, IEEE-754 Decoding, and Variable-Length Encoding Savings
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Comp-A3, Computer Architecture — National Exams, May 2016. Closed-book, 3 hours; six questions of equal value (20 marks each); FIVE constitute a complete exam (all six answered below as a complete study resource).
Reference texts: Patterson & Hennessy, Computer Organization and Design, 6th ed. — memory hierarchy & cache design (Q1a, Q2a, Q3a, Q5a), bus/data-transfer performance (Q1c), instruction-level parallelism (Q2c), instruction encoding & RISC/CISC tradeoffs (Q3b, Q4c), IEEE-754 floating point and memory technology (Q4a–b), branch prediction and addressing modes (Q6a–b); Mano & Ciletti, Digital Design, 6th ed. — control-unit design (Q1b, Q5c–d), unsigned binary division hardware (Q3c), reverse-Polish/stack notation (Q5b), and shift operations (Q6c); Stallings, Data and Computer Communications — programmed vs. interrupt-driven I/O (Q2b).
Given. (a) The general categories of volatile and non-volatile memory. (b) Two IEEE-754 single-precision bit patterns, $S{+}E(8){+}M(23)$. (c) An ISA with 56 registers, 221 opcodes, 16-bit immediates, and a program whose instructions are 20%/30%/25%/25% split across four operand-format types, with all instructions rounded up to a multiple of 8 bits.
Find. (a) The volatile/non-volatile distinction with examples. (b) The decimal value each bit pattern represents. (c)(1) The bit width of each instruction type. (c)(2) The memory saved by variable-length vs. fixed-length encoding.
Approach. (a) define by whether stored state survives loss of power; (b) apply $(-1)^S\times1.M\times2^{E-127}$; (c) size the opcode field from $\lceil\log_2 221\rceil$, each register field from $\lceil\log_2 56\rceil$, add the fixed 16-bit immediate where present, round each type up to the next multiple of 8, then compare a weighted average (variable-length) against the single worst-case width (fixed-length).
Part (a) — volatile vs. non-volatile memory.Volatile memory requires continuous power to retain its stored data; the instant power is removed, the contents are lost. Examples: SRAM (used for CPU caches/register files — each bit is a cross-coupled latch that needs power to hold state) and DRAM (used for main memory — each bit is a capacitor charge that leaks and must also be periodically refreshed even while powered). Non-volatile memory retains its stored data indefinitely with no power applied. Examples: ROM/PROM (mask- or fuse-programmed, unchangeable after manufacture/programming), EPROM/EEPROM/flash (electrically or UV-erasable and reprogrammable, used for firmware/BIOS and, for flash, for SSDs and USB drives), and magnetic/optical media (hard disks, magnetic tape, CDs/DVDs, which store data as persistent magnetic or optical states). The defining test is simple: disconnect power — volatile memory forgets, non-volatile memory remembers.
Part (b) — IEEE-754 decoding. The value is $(-1)^S\times(1+M/2^{23})\times2^{E-127}$, with the bias 127 subtracted from the stored 8-bit exponent.
Part (c) — instruction bit widths and variable- vs. fixed-length memory savings. The opcode field must distinguish 221 instructions, needing $\lceil\log_2 221\rceil=8$ bits (since $2^7=128<221\le256=2^8$); each register field must address 56 registers, needing $\lceil\log_2 56\rceil=6$ bits (since $2^5=32<56\le64=2^6$); each immediate field is the given fixed 16 bits.
Type
Fields
Raw bits
Rounded to mult. of 8
Weight
1 (20%)
opcode + 1 in-reg + 1 out-reg
$8+6+6=20$
$\boxed{24\ \text{bits}}$
0.20
2 (30%)
opcode + 2 in-reg + 1 out-reg
$8+6+6+6=26$
$\boxed{32\ \text{bits}}$
0.30
3 (25%)
opcode + 1 in-reg + 1 out-reg + immediate
$8+6+6+16=36$
$\boxed{40\ \text{bits}}$
0.25
4 (25%)
opcode + 1 out-reg + immediate
$8+6+16=30$
$\boxed{32\ \text{bits}}$
0.25
(1) Each raw field count is rounded UP to the next multiple of 8 bits, since the ISA requires whole bytes per instruction: 20→24, 26→32, 36→40, 30→32 bits, as tabulated above. (2) A fixed-length encoding must make every instruction as wide as the WIDEST type actually needed, i.e. $\boxed{40\ \text{bits}}$ (5 bytes) per instruction regardless of type. A variable-length encoding instead uses each type's own rounded width, so the average bits per instruction over the given mix is
$$\bar b_{\text{var}}=0.20(24)+0.30(32)+0.25(40)+0.25(32)=4.8+9.6+10.0+8.0=\boxed{32.4\ \text{bits}}$$
The saving per instruction is $40-32.4=7.6$ bits, i.e.
$$\frac{40-32.4}{40}\times100\%=\boxed{19\%}$$
so the variable-length program occupies 19% less memory than the fixed-length version of the same program (equivalently, 7.6 bits saved per instruction on average, or $7.6N$ bits total for a program of $N$ instructions).
Final results — Question 4
Part
Result
(a) volatile vs. non-volatile
Volatile (SRAM, DRAM) loses data without power; non-volatile (ROM, EEPROM/flash, magnetic/optical) retains it
(b)(1)
$-0.046875$
(b)(2)
$15{,}393{,}162{,}788{,}864$
(c)(1) bit widths
Type 1: 24 bits; Type 2: 32 bits; Type 3: 40 bits; Type 4: 32 bits