AC steady-state analysis and phasor diagram: 22-Elec-A1 Circuits, May 2017, Q4

Question 4: AC steady-state analysis and phasor diagram [6 + 6 + 8]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $v_s=100\sin377t\text{ V}$ (so $\omega=377\text{ rad/s}$), a series $10\,\Omega$, then $L=0.5\text{ H}$ in parallel with $5\,\Omega$, then a series capacitor $C=20\,\mu\text{F}$ across which $v_c$ is measured. $i_s$ is the series (source) current.

Element	Impedance at $\omega=377$
$L=0.5\text{ H}$	$Z_L=j\omega L=j188.5\,\Omega$
$5\,\Omega$	$5\,\Omega$
$L\,\\|\,5\,\Omega$	$4.998+j0.133\,\Omega$
$C=20\,\mu\text{F}$	$Z_C=1/(j\omega C)=-j132.63\,\Omega$
Series $10\,\Omega$	$10\,\Omega$

Find. the time functions $i_s(t)$, $v_c(t)$, and the phasor diagram relating $\overline{V_s},\overline{I_s},\overline{V_c}$.

[Figure not reproduced: Figure 4 — redrawn. Series loop: source → $10\,\Omega$ → ($L\,\|\,5\,\Omega$) → $C$ → back to source; $v_c$ is the capacitor voltage. Sine (peak) reference: $\overline{V_s}=100\angle0^\circ\text{ V}$. See the official exam paper.]

Approach. Convert every element to an impedance at $\omega=377$, combine the single series loop, get $\overline{I_s}=\overline{V_s}/Z_{tot}$, then $\overline{V_c}=\overline{I_s}\,Z_C$; return to the time domain with the sine reference.

(a) Parallel block $L\,\|\,5\,\Omega$. $$Z_p=\frac{(j188.5)(5)}{5+j188.5}=4.998+j0.133\,\Omega\approx5.0\angle1.5^\circ\,\Omega$$ (the huge inductive reactance makes the $5\,\Omega$ dominate).
(a) Total series impedance. $$Z_{tot}=10+Z_p+Z_C=10+(4.998+j0.133)+(-j132.63)=15.0-j132.5\,\Omega=133.34\angle-83.54^\circ\,\Omega.$$ The loop is strongly capacitive.
(a) Source current. $$\boxed{\overline{I_s}=\frac{100\angle0^\circ}{133.34\angle-83.54^\circ}=0.75\angle83.54^\circ\text{ A}\ \Rightarrow\ i_s(t)=0.75\sin(377t+83.5^\circ)\text{ A}.}$$ The current leads the source voltage, as expected for a net capacitive circuit.
(a) Capacitor voltage. $$\overline{V_c}=\overline{I_s}\,Z_C=(0.75\angle83.54^\circ)(132.63\angle-90^\circ)=99.46\angle-6.46^\circ\text{ V},$$ $$\boxed{v_c(t)=99.46\sin(377t-6.46^\circ)\text{ V}.}$$
(b) Phasor diagram. $\overline{V_s}=100\angle0^\circ$ along the reference; $\overline{I_s}=0.75\angle83.5^\circ$ leads it by almost $90^\circ$; $\overline{V_c}=99.46\angle-6.5^\circ$ lags $\overline{V_s}$ slightly (it trails $\overline{I_s}$ by exactly $90^\circ$). Drawn to relative scale below (current magnified for visibility).

Phasor diagram (Q4b). $\overline{I_s}$ leads $\overline{V_s}$ by $83.5^\circ$; $\overline{V_c}$ lags $\overline{I_s}$ by $90^\circ$, landing at $-6.5^\circ$. The current phasor is drawn to a larger scale ($1\text{ A}\!\to\!$ full length) than the voltages ($100\text{ V}\!\to\!$ full length).

Quantity	Value
$Z_{tot}$	$133.34\angle-83.54^\circ\,\Omega$
$i_s(t)$	$0.75\sin(377t+83.5^\circ)\text{ A}$
$v_c(t)$	$99.46\sin(377t-6.46^\circ)\text{ V}$

Topic: Single-frequency AC steady-state analysis with phasors and impedances.

Key relations: $Z_L=j\omega L$, $Z_C=1/(j\omega C)=-j/(\omega C)$; series $Z_{tot}=\sum Z$; Ohm’s law in phasors $\overline V=\overline I\,Z$; recovery $x(t)=|\overline X|\sin(\omega t+\angle\overline X)$ under a sine reference.

Why this works: At one frequency every derivative becomes multiplication by $j\omega$, so each element is a constant complex impedance and the whole loop obeys the same algebra as a dc resistive circuit. The capacitor’s $-90^\circ$ impedance is what makes $\overline{V_c}$ lag $\overline{I_s}$ by exactly a quarter cycle. Because $|Z_C|\gg|Z_p|,10\,\Omega$, the loop is dominated by the capacitor: $\overline{I_s}$ leads by nearly $90^\circ$ and almost all the source voltage appears across $C$.

Common pitfall: mixing sine and cosine references (a $90^\circ$ error) — keep the sine reference set by $100\sin377t$; and using $j\omega C$ where $1/(j\omega C)$ is meant for the capacitor impedance.

Source: Sadiku, Fundamentals of Electric Circuits, §9.4–9.5 (impedance, phasors) and §10.1 (AC circuit analysis).

Question 4 of 6: AC steady-state analysis and phasor diagram

Question 4: AC steady-state analysis and phasor diagram [6 + 6 + 8]