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22-Elec-A5 Electronics · Undated paper

Question 3 of 5: Common-emitter amplifier design

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exams — Electronics, 16-Elec-A5. Closed-book; one approved Casio/Sharp calculator. Answer all five questions; each worth 20 marks. Op-amps assumed ideal with ±15 V supplies unless stated; ground and chassis common. Duration 3 hours.

Reference texts. A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (diodes ch. 4; MOSFET & BJT amplifiers ch. 5–8; MOS inverters ch. 13–14) — primary; C. K. Alexander & M. Sadiku, Fundamentals of Electric Circuits, 7th ed. (Thévenin equivalents, ch. 4) for the resistive-bridge question.

The question pages identify this paper as the 16-Elec-A5 Electronics, May 2019 sitting.

Question 3: Common-emitter amplifier design

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A CE stage on $\pm5\text{ V}$ rails with the emitter split into $R_{E1}$ (un-bypassed) and $R_{E2}$ (bypassed by $C_E$); $C_1,C_2$ couple the source and load.

Given data
$\beta$$100$$V_{BE(on)}$$0.7\text{ V}$
$R_S$$500\ \Omega$$R_B$$100\text{ k}\Omega$
$I_E$$0.2\text{ mA}$$v_s\to v_o$$12\text{ mV}_{pp}\to0.4\text{ V}_{pp}$

Find. $R_C$, $R_{E1}$ and $R_{E2}$ meeting the overall gain and a sensible bias point.

+5 V R C Q 1 C₂ v o C₁ R_S v s R B R E1 R E2 −5 V C E I E
Common-emitter stage: $R_B$ biases the base, $R_C$ is the collector load, $R_{E1}$ provides a.c. degeneration while $R_{E2}$ (bypassed by $C_E$) carries the d.c. emitter current to the $-5\text{ V}$ rail.

Approach. The overall required gain is fixed; set the d.c. bias from $I_E$, choose $R_C$ to centre the collector for maximum symmetric swing, then solve $R_{E1}$ (the only a.c. emitter resistance, since $R_{E2}$ is bypassed) for the gain and take $R_{E2}$ as the remainder of the d.c. emitter chain.

  1. Required gain. $|A_v|=\dfrac{v_o}{v_s}=\dfrac{0.4\text{ V}}{12\text{ mV}}=33.3\text{ V/V}$.
  2. D.c. bias. $I_B=\dfrac{I_E}{\beta+1}=1.98\ \mu\text{A}$, $I_C=\beta I_B=0.198\text{ mA}$. Base current is drawn through $R_B$ from ground, so $V_B=-I_BR_B=-0.198\text{ V}$ and $V_E=V_B-V_{BE}=-0.898\text{ V}$.
  3. Small-signal constants. $r_e=\dfrac{V_T}{I_E}=\dfrac{25\text{ mV}}{0.2\text{ mA}}=125\ \Omega$, $g_m=\dfrac{I_C}{V_T}=7.92\text{ mA/V}$, $r_\pi=\dfrac{\beta}{g_m}=12.6\text{ k}\Omega$.
  4. Emitter chain (d.c.). The full emitter current flows through $R_{E1}+R_{E2}$ to $-5\text{ V}$: $R_{E1}+R_{E2}=\dfrac{V_E-(-5)}{I_E}=\dfrac{4.102\text{ V}}{0.2\text{ mA}}=20.5\text{ k}\Omega$.
  5. Collector resistor (max swing). Centre $V_C$ between $V_{CC}$ and the saturation floor $V_E+V_{CE(sat)}$: $V_C=\tfrac12\big(5+(-0.898+0.2)\big)=2.15\text{ V}\Rightarrow \boxed{R_C=\dfrac{5-2.15}{0.198\text{ mA}}=14.4\text{ k}\Omega}$.
  6. Solve $R_{E1}$ for gain. With $R_{E2}$ bypassed the a.c. emitter resistance is $R_{E1}$, and $$A_v=\frac{R_B\Vert[r_\pi+(\beta{+}1)R_{E1}]}{R_S+R_B\Vert[r_\pi+(\beta{+}1)R_{E1}]}\cdot\frac{\beta R_C}{r_\pi+(\beta{+}1)R_{E1}}=33.3.$$ Solving numerically gives $\boxed{R_{E1}\approx295\ \Omega}$ (so $R_{E1}+r_e\approx420\ \Omega$, $|v_o/v_b|\approx R_C/(R_{E1}+r_e)\approx34$, trimmed by the input divider).
  7. Bypassed emitter resistor. $\boxed{R_{E2}=20.5\text{ k}\Omega-295\ \Omega\approx20.2\text{ k}\Omega}$.
Question 3 design
$R_C$$R_{E1}$$R_{E2}$$I_C$$V_B$$V_E$$V_C$
$14.4\text{ k}\Omega$$295\ \Omega$$20.2\text{ k}\Omega$$0.198\text{ mA}$$-0.198\text{ V}$$-0.898\text{ V}$$2.15\text{ V}$
Check: the design is not unique — only the a.c. gain and the d.c. emitter chain are constrained. The collector node was centred for maximum symmetric swing ($V_C=2.15\text{ V}$); $V_T=25\text{ mV}$ assumed. Nearest E24 values ($R_C=15\text{ k}\Omega$, $R_{E1}=300\ \Omega$, $R_{E2}=20\text{ k}\Omega$) hold the gain within a few percent.