Question 1 of 5: MOSFET Differential Pair with Current‑Source Loads

Question 1: MOSFET Differential Pair with Current‑Source Loads (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A matched NMOS source‑coupled pair M1–M2 biased by a tail source I_bias and loaded by two matched PMOS current sources M3–M4 whose gates share the fixed bias V_bias; the output is taken single‑ended at the drain of M2.

Find. The single‑ended differential gain $v_{OUT}/v_{IN}$, the common‑mode input resistance $R_{icm}$, the common‑mode input range, and the common‑mode rejection ratio expressed in dB.

Approach. Fix the operating point from the saturation law, extract $g_m$ and $r_o$, then use the differential half‑circuit for the gain, the saturation‑edge conditions on M1/M2 and on the tail for the input range, and the common‑mode half‑circuit (degeneration $2R_{SS}$) for the rejection ratio.

1. Part (a) — split the tail current between the two halves. The pair is symmetric, so each input device carries half the tail current, $I_{D1}=I_{D2}=I_{bias}/2=0.5\ \text{mA}$. Inverting the saturation law $I_D=\tfrac12 K V_{ov}^{2}$ gives the overdrive $V_{ov}=\sqrt{2I_D/K}=\sqrt{2(0.5)/0.5}=1.414\ \text{V}$, so $V_{GS}=V_{TH}+V_{ov}=2.414\ \text{V}$.
2. Extract the small‑signal parameters. $g_m=K V_{ov}=\sqrt{2KI_D}=\sqrt{2(0.5\times10^{-3})(0.5\times10^{-3})}=0.707\ \text{mA/V}$ and $r_o=1/(\lambda I_D)=1/(0.02\times0.5\times10^{-3})=100\ \text{k}\Omega$. M3 and M4 carry the same $0.5\ \text{mA}$ and share $\lambda$, so $r_{o3}=r_{o4}=100\ \text{k}\Omega$ as well.
3. Load the output node. M3 and M4 have their gates tied to a fixed potential, so each behaves as a current source of output resistance $r_{o4}$; the drain of M2 therefore sees $R_{out}=r_{o2}\parallel r_{o4}=100\parallel100=50\ \text{k}\Omega$.
4. Apply the differential half‑circuit. Only half of $v_{IN}$ appears on each gate, so the single‑ended output swings by $\tfrac12 g_m R_{out}$ per volt of differential input: $$\frac{v_{OUT}}{v_{IN}}=\tfrac12 g_m\left(r_{o2}\parallel r_{o4}\right)=\tfrac12(0.707\times10^{-3})(50\times10^{3})=\boxed{+17.7\ \text{V/V}\quad(24.9\ \text{dB})}$$ The sign is positive because the output node is the drain of M2, whose gate is driven by $-v_{IN}/2$; the inverting stage and the inverting drive cancel.
5. Part (b) — look into the gates. The inputs land directly on the gate oxide of M1 and M2. A MOSFET gate passes no d.c. current, so no current is drawn when both gates are moved together and $$R_{icm}=\boxed{\infty\ (\text{ideally})}$$ In practice the limit is gate leakage (fractions of a pA, i.e. $10^{12}\ \Omega$ and above) shunted at signal frequencies by the common‑mode input capacitance $C_{gs}+C_{gb}$ of the two devices — the resistance is finite only in the sense that any real insulator is.
6. Part (c) — upper end of the common‑mode range. The PMOS loads set the drain potential. Their overdrive is fixed by the printed bias: $|V_{ov3}|=V_{DD}-V_{bias}-|V_{TH}|=10-6-1=3\ \text{V}$, so M3/M4 stay saturated only while their drains sit at or below $V_{DD}-|V_{ov3}|=7\ \text{V}$. M1/M2 remain saturated while $V_D\ge V_{ICM}-V_{TH}$, hence $$V_{ICM,\max}=V_{DD}-|V_{ov3}|+V_{TH}=10-3+1=\boxed{+8.0\ \text{V}}$$
7. Lower end of the common‑mode range. Coming down, the common source node follows the inputs at $V_{ICM}-V_{GS}$ and must leave the tail source enough compliance: $V_{ICM,\min}=-V_{SS}+V_{CS}+V_{GS}$. Realising the tail as one saturated NMOS carrying $I_{bias}$ needs $V_{CS}=\sqrt{2I_{bias}/K}=\sqrt{2(1)/0.5}=2\ \text{V}$, giving $V_{ICM,\min}=-10+2+2.414=\boxed{-5.59\ \text{V}}$, i.e. a usable window $-5.59\ \text{V}\le V_{ICM}\le+8.0\ \text{V}$ (13.6 V wide). With the idealised tail actually drawn, $V_{CS}=0$ and the floor drops to $-7.59\ \text{V}$.
8. Part (d) — put a resistance on the tail. Common‑mode rejection is finite only because the tail source is not ideal. Modelling it as the same saturated NMOS carrying $I_{bias}$, $R_{SS}=1/(\lambda I_{bias})=1/(0.02\times10^{-3})=50\ \text{k}\Omega$.
9. Common‑mode half‑circuit. Driving both gates together, each half is a source‑degenerated stage with $2R_{SS}$ in its source and $r_{o4}$ as its drain load: $$A_{cm}=\frac{-g_m r_{o4}}{1+2g_mR_{SS}+\dfrac{r_{o4}+2R_{SS}}{r_{o2}}}=\frac{-70.7}{1+70.7+2}=-0.959$$ Degeneration has cut the transconductance by a factor of about 72, which is the whole mechanism of rejection.
10. Form the ratio. $$\text{CMRR}=\left|\frac{A_d}{A_{cm}}\right|=\frac{17.68}{0.959}=18.4\;\Longrightarrow\;\text{CMRR}_{\text{dB}}=20\log_{10}(18.4)=\boxed{25.3\ \text{dB}}$$ The frequently quoted shortcut $\text{CMRR}\approx g_mR_{SS}=35.4$ (31.0 dB) is optimistic here because it assumes the same drain load in both modes, whereas the differential gain is loaded by $r_{o2}\parallel r_{o4}=50\ \text{k}\Omega$ and the common‑mode gain by $r_{o4}=100\ \text{k}\Omega$ alone.