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22-Mec-A5 Electrical and Electronics Engineering · December 2017

Question 1 of 8: Transistor Amplifier — Bias Design and Load Lines

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

Paper format. PEO / Engineers Canada National Examinations, December 2017 — 16-Mec-A5, Electrical & Electronics Engineering (Mechanical Engineering discipline). Three hours, closed book, one approved Casio or Sharp calculator. Eight questions; any five constitute a complete paper and each question is of equal value, so each counted question carries 20 marks. All eight questions are solved below, because this set is a study resource rather than an exam script. The front page prints the constants $\pi = 3.14159$, $1\text{ hp} = 746\text{ W}$ and $\mu_0 = 4\pi\times10^{-7}\text{ H m}^{-1}$; all three are used exactly as given (this sitting prints $\mu_0$ with the correct negative exponent).

Reference texts. A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. (BJT biasing and load lines, op-amp frequency response); M. M. Mano and M. D. Ciletti, Digital Design, 6th ed. (universal-gate synthesis, DeMorgan reduction); S. J. Chapman, Electric Machinery Fundamentals, 5th ed. (dc machines, transformer magnetic circuits, induction-motor testing and slip); C. K. Alexander and M. N. O. Sadiku, Fundamentals of Electric Circuits, 7th ed. (phasor analysis, power factor, first-order transients); W. H. Hayt and J. A. Buck, Engineering Electromagnetics, 9th ed. (magnetic circuits and induced emf).

the gated-logic array, the transformer magnetic circuit, the op-amp band-pass Bode question, the RC transient and the parallel ac network as printed in December 2014; and the induction-motor slip / speed-torque question as printed in December 2016. The full working is transcribed in place below rather than cross-referenced, so this paper stands on its own as a study document.

Question 1: Transistor Amplifier — Bias Design and Load Lines (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single-stage common-emitter amplifier with voltage-divider bias, an emitter bypass capacitor and a capacitively coupled load, with the component values listed below.

Given data
QuantitySymbolValue
Supply voltage$V_{CC}$15 V
Lower divider resistor (base to ground)$R_1$10 k$\Omega$
Upper divider resistor (base to $V_{CC}$)$R_2$30 k$\Omega$
DC current gain$\beta$100
Required collector current$I_C$2 mA
Required collector–emitter voltage$V_{CE}$6 V
Load resistance (ac coupled)$R_L$3 k$\Omega$
Input base-current signal$i_b$$10 \sin \omega t\ \mu$A
Base–emitter drop (silicon, assumed)$V_{BE}$0.7 V

Find. The bias resistors $R_E$ and $R_C$ that place the quiescent point at $I_C = 2$ mA and $V_{CE} = 6$ V, the dc and ac load lines on the output characteristics, and the peak output voltage produced by the given signal current.

VCC = 15 VR2 = 30 kΩR1 = 10 kΩibRCRERL = 3 kΩvo
Figure 1 — Transistor circuit: voltage-divider bias, bypassed emitter resistor, capacitively coupled load.

Approach. Replace the base divider by its Thévenin equivalent to fix the base potential, walk KVL down the base–emitter loop for $R_E$ and along the collector–emitter loop for $R_C$, then draw the two load lines — the dc line set by $R_C + R_E$ and the ac line set by $R_C \parallel R_L$ through the quiescent point.

  1. Fix the base potential from the divider. With negligible base loading the divider acts as an unloaded potentiometer, so $$V_B = V_{CC}\,\frac{R_1}{R_1+R_2} = 15 \times \frac{10}{10+30} = 3.75\ \text{V}.$$ The assumption is worth checking: the Thévenin resistance is $R_1 \parallel R_2 = 7.5\ \text{k}\Omega$ and the base current is only $I_B = I_C/\beta = 20\ \mu\text{A}$, so the drop it causes is $20\ \mu\text{A} \times 7.5\ \text{k}\Omega = 0.15\ \text{V}$, about 4 % of $V_B$. The divider is stiff enough for the standard design equations.
  2. Convert collector current to emitter current. The emitter carries both the collector and base currents, so $$I_E = I_C\,\frac{\beta+1}{\beta} = 2\ \text{mA} \times \frac{101}{100} = 2.02\ \text{mA}.$$
  3. Solve the base–emitter loop for $R_E$. Subtracting the base–emitter drop from the base potential leaves the emitter potential $V_E = V_B - V_{BE} = 3.75 - 0.7 = 3.05\ \text{V}$, and this appears across $R_E$: $$R_E = \frac{V_E}{I_E} = \frac{3.05}{2.02\times 10^{-3}} = \boxed{1.51\ \text{k}\Omega}$$
  4. Solve the collector–emitter loop for $R_C$. The collector sits $V_{CE}$ above the emitter, $V_C = V_E + V_{CE} = 3.05 + 6 = 9.05\ \text{V}$, and the remainder of the supply is dropped across $R_C$: $$R_C = \frac{V_{CC}-V_C}{I_C} = \frac{15-9.05}{2\times 10^{-3}} = \boxed{2.98\ \text{k}\Omega}$$ Nearest standard 5 % values would be 1.5 k$\Omega$ and 3.0 k$\Omega$, which shift the operating point by well under a tenth of a volt.
  5. Draw the dc load line. For direct current both $R_C$ and $R_E$ are in the collector–emitter path, so $$V_{CE} = V_{CC} - I_C\,(R_C+R_E).$$ The line runs between the open-circuit intercept $V_{CE} = 15\ \text{V}$ at $I_C = 0$ and the saturation intercept $I_C = 15/(2975+1510) = 3.34\ \text{mA}$ at $V_{CE} = 0$, passing through the quiescent point $(6\ \text{V},\ 2\ \text{mA})$ as designed.
  6. Draw the ac load line. At signal frequencies the bypass capacitor shorts $R_E$ and the coupling capacitor connects $R_L$ in parallel with $R_C$, so the collector works into $$r_{ac} = R_C \parallel R_L = \frac{2975 \times 3000}{2975+3000} = 1.494\ \text{k}\Omega.$$ The ac line is steeper than the dc line and must pass through the same quiescent point, giving intercepts $V_{CE} = 6 + (2\ \text{mA})(1.494\ \text{k}\Omega) = 8.99\ \text{V}$ and $I_C = 2 + 6/1.494 = 6.02\ \text{mA}$.
  7. Estimate the output voltage. The signal collector current is $\beta$ times the signal base current, $i_c = \beta\, i_b = 100 \times 10\ \mu\text{A} = 1\ \text{mA}$ peak, and it develops the output across the ac load: $$v_o = i_c \, r_{ac} = (1\times10^{-3})(1494) = \boxed{1.49\ \text{V peak}}$$ that is $2.99\ \text{V}$ peak-to-peak, or $1.06\ \text{V rms}$, inverted with respect to the input.
  8. Confirm the swing is not clipped. Travelling up the ac load line the transistor reaches cut-off after $I_C\,r_{ac} = 2.99\ \text{V}$, and travelling down it reaches saturation after $V_{CE} = 6\ \text{V}$. The required 1.49 V peak fits inside both limits, so the stage is operating linearly — though the positive half-cycle has only twice the headroom it needs, which is the practical limit on this bias point.
VCE (V)IC(mA)024681012141601234567IB = 10 μAIB = 20 μAIB = 30 μAIB = 40 μAIB = 50 μAIB = 60 μAdc load lineac load lineQoutput swing 1.49 V peak
Output characteristics with the dc load line (slope set by $R_C+R_E$), the steeper ac load line (slope set by $R_C \parallel R_L$), the quiescent point Q and the signal swing.
Final results — Question 1
QuantityResult
Base (Thévenin) potential $V_B$3.75 V
Emitter current $I_E$2.02 mA
Emitter resistor $R_E$1.51 k$\Omega$
Collector resistor $R_C$2.98 k$\Omega$
dc load-line intercepts15 V and 3.34 mA
ac load resistance $r_{ac}$1.494 k$\Omega$
ac load-line intercepts8.99 V and 6.02 mA
Signal collector current $i_c$1.00 mA peak
Output voltage $v_o$1.49 V peak (2.99 V p–p), inverted
Check — assumptions. $V_{BE} = 0.7$ V is taken as the silicon room-temperature value (the paper does not state it), and the Early effect is neglected so the characteristics are drawn flat. Both are the conventional closed-book assumptions and neither changes the answers by more than a few percent.
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