22-Mec-B4 Integrated Manufacturing Systems · May 2017

Question 2 of 6: PLC Design for a Four-Test Inspection Cell

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Question 2: PLC Design for a Four-Test Inspection Cell (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A single-lane indexing conveyor carries each part past four inspection stations; the design data are collected below.

Find. The controller design: an input/output allocation, the Boolean sort equations for the three bin gates in minimum form, the ladder rungs that implement the motor seal-in circuit, the 100 s dwell and the indexing, and the resulting cell throughput.

Approach. Treat the sortation as a purely combinational problem in the four pass bits, minimise it by inspection of the pass count, then wrap the combinational core in the sequential logic — a seal-in motor circuit, an on-delay timer for the dwell, and a shift register that carries each part's accumulating results along the conveyor with it.

1. Allocate the input and output points. Each test head returns one discrete bit, so a small controller with eight inputs and four outputs is sufficient. Inputs: PB1 start, normally open; PB2 stop, normally closed; OL motor overload contact, normally closed; PRS part-present photo-eye; and the four test results A, B, C, D, each true when that test is passed. Outputs: M the belt motor starter, and SOL1, SOL2, SOL3 the three bin diverter solenoids. Internal addresses hold the dwell timer T1, the index pulse IDX, the four-bit result file and one internal relay used below.
2. Classify the sixteen input states by pass count. With four independent pass/fail bits there are $2^{4}=16$ states, and the specification partitions them only by how many bits are true. Writing $n=A+B+C+D$ for the pass count, the specification gives $$n = 4 \Rightarrow \text{bin 3},\qquad n \in \{2,3\} \Rightarrow \text{bin 1}, \qquad n = 1 \Rightarrow \text{bin 2}.$$ Counting the states in each class gives one state for bin 3, six with $n=2$ plus four with $n=3$, that is ten states for bin 1, and four states for bin 2. The sixteenth state, $n=0$, is not assigned by the question.
3. Write the bin 3 equation. A perfect unit is the single minterm in which every test bit is true, so no minimisation is possible or needed: $$\boxed{\;\text{SOL3} = A \cdot B \cdot C \cdot D\;}$$ This is one four-input AND, or four series contacts on a rung.
4. Build the shared "two or more" network. Both of the remaining bins are defined against the threshold of two passes, so it pays to generate that condition once as an internal relay. At least two of four bits are true exactly when some pair of them is true, which is the OR of the six two-bit products: $$P_2 = AB + AC + AD + BC + BD + CD .$$ Six two-input AND terms replace the ten-minterm expansion that a naive sum-of-products would produce, and the same network serves both remaining outputs. Enumerating all sixteen states confirms that $P_2$ is true for exactly the ten states with $n \ge 2$.
5. Write the bin 1 and bin 2 equations from the threshold. Bin 1 wants two or three passes, which is "at least two, but not all four"; bin 2 wants exactly one, which is "at least one, but not two or more". Hence $$\boxed{\;\text{SOL1} = P_2 \cdot \overline{A B C D}, \qquad \text{SOL2} = (A + B + C + D)\cdot \overline{P_2}\;}$$ Because SOL3 is already the product $ABCD$, the complement term in SOL1 is simply a normally closed contact on the SOL3 output, and no extra gate is needed. A state-by-state check of all sixteen combinations confirms that the three gates are mutually exclusive and that exactly one fires whenever at least one test has been passed.
6. Handle the unassigned all-fail state. The question assigns no bin to a part that passes nothing. The equations above leave all three solenoids de-energised in that state, so such a part is not diverted and runs off the end of the belt into the reject chute, which is the safe default: a scrap part is never mixed into a graded bin. The alternative reading is treated in the callout following this answer.
7. Close the motor circuit with a seal-in rung. The start pushbutton is momentary and normally open, so the motor output must latch itself: $$M = (\text{PB1} + M)\cdot \text{PB2} \cdot \text{OL}.$$ PB2 is wired normally closed and programmed as an examine-if-closed contact, so a broken wire to the stop button drops the motor — the fail-safe convention. The overload contact is in series for the same reason.
8. Time the dwell and the index. An on-delay timer is started by the part-present photo-eye once the belt has stopped; its done bit drives the index output that advances the belt by one station pitch: $$T_1 = \text{TON}(\text{preset } 100\ \text{s}), \qquad \text{IDX} = T_1/\text{DN}.$$ The rising edge of IDX is also the clock for the shift register, so the four result bits move one place each time the part moves one station. Without that shift register the controller would sort each part on whatever bits happened to be present when it reached the discharge, and with up to four parts on the belt at once the results would be attributed to the wrong pieces.
9. Compute the cell cycle time and throughput. Adding the assumed 5 s index to the 100 s dwell gives a station cycle of $$t_c = 100 + 5 = 105\ \text{s},$$ and since the four stations operate simultaneously on four different parts the cell delivers one finished part per station cycle: $$\boxed{\;R_p = \frac{3600}{105} = 34.29\ \text{parts/h}\;}$$ A part is resident in the cell for $4 \times 105 = 420$ s, that is 7.0 min.