25-Nav-B6 Ocean Engineering and Offshore Structures · Undated paper
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Paper format. PEO National Examinations, May 2019 — 98-Mar-B6, printed for Electrical & Electronics Engineering / Mechanical Engineering candidates. Three hours, closed book, two approved calculators (Casio or Sharp). Eight questions of equal value; any five constitute a complete paper, and only the first five appearing in the answer book are marked. Constants supplied on the front page: $\pi = 3.14159$, $1\ \text{hp} = 746\ \text{W}$. All eight questions are solved here so the solutions cover whichever five a candidate chooses.
This paper is listed under 25-Nav-B6 “Ocean Engineering and Offshore Structures”, but the printed paper is headed 98-Mar-B6 (front page: 98-Elec-B6) and every question is Electrical & Electronics Engineering content (BJT current-mirror analysis, combinational logic, a linear dc machine, a gapped/parallel-path transformer magnetic circuit, a three-op-amp instrumentation amplifier, an induction-motor dc test and slip calculation, an RC transient/frequency-response network, and industrial power-factor correction) — zero naval-architecture or ocean-engineering content. Solved as the exam actually printed.
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Given. Part I supplies a network of four 2-input NAND gates wired so that the first gate output $C$ feeds both of the second-rank gates, whose outputs $D$ and $E$ drive the final gate. Part II supplies nothing but the requirement that a 2-input exclusive-OR be realised from 2-input NOR gates alone.
Find. For Part I the Boolean expression at $F$, its simplest form and the equivalent single gate, plus the full truth table at $C$, $D$, $E$ and $F$; for Part II the truth table, the algebraic expression, a NOR-realisable form of it and the resulting gate array.
[Figure not reproduced: Figure 2 — Combinational logic circuit. All four gates are 2-input NAND (flat back with an output bubble), read directly from the examination drawing. See the official exam paper.]
Approach. Label each gate output in turn and propagate the NAND function forward, then apply DeMorgan's theorem to the final expression and recognise the standard form. For Part II, start from the canonical sum of products for exclusive-OR and drive it into a form built only from OR-then-invert operations, which is exactly what a NOR gate performs.
Part I [a] — the general expression. Taking the gates in order and writing $X'$ for the complement of $X$:
Part I [b] — simplification. Apply DeMorgan's theorem to the output gate first, which converts the NAND of two complements into a plain OR:
The network is therefore an exclusive-OR, and the answer to the question asked in [b] is yes — a single 2-input EOR (XOR) gate can replace all four NAND gates. This four-NAND arrangement is the classical minimum-gate XOR built from a single universal gate type.
Part I [c] — truth table. Evaluating each node for the four input combinations confirms the algebra:
| $A$ | $B$ | $C=\overline{AB}$ | $D=\overline{AC}$ | $E=\overline{BC}$ | $F=\overline{DE}$ |
|---|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 0 |
The $F$ column is 0, 1, 1, 0 — high only when the inputs differ, which is the exclusive-OR signature obtained algebraically.
Part II [d] — truth table for the EOR gate.
| $A$ | $B$ | $Y = A \oplus B$ |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Part II [e] — the general expression. Reading the two rows for which the output is 1 gives the canonical sum of products $$Y = \overline{A}B + A\overline{B}.$$
Part II [f] — conversion to NOR form. A NOR gate ORs its inputs and inverts, so the target is an expression built entirely from $\overline{X+Y}$ operations. The key manoeuvre is to produce each of the two product terms as a NOR of an input with the NOR of both inputs:
The realisation needs five 2-input NOR gates, which is the minimum for this function using NOR alone.
| Item | Result |
|---|---|
| Part I [a] general expression | $F = \overline{\;\overline{A\,\overline{AB}}\cdot\overline{B\,\overline{AB}}\;}$ |
| Part I [b] simplified | $F = \overline{A}B + A\overline{B} = A \oplus B$ |
| Part I [b] single equivalent gate | One 2-input exclusive-OR (EOR) gate — yes |
| Part I [c] output column $F$ | 0, 1, 1, 0 for $AB$ = 00, 01, 10, 11 |
| Part II [e] expression | $Y = \overline{A}B + A\overline{B}$ |
| Part II [f] NOR form | $Y = \overline{\,\overline{A+\overline{A+B}}+\overline{B+\overline{A+B}}\,}$ |
| Part II [g] gate count | Five 2-input NOR gates (the last one wired as an inverter) |