Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
98-Phys-A5 — Semiconductor Devices & Circuits — National Exams, May 2014
3 hours duration. Closed book exam (useful constants and equations annexed to the paper). Any FIVE (5) of the SEVEN (7) questions constitute a complete exam paper; all seven are answered here as a complete study resource.
Reference texts: A. S. Sedra & K. C. Smith, Microelectronic Circuits, 8th ed. (diode I–V characteristics and junction physics Ch. 3–4, op-amp circuits and active filters Ch. 2–12, BJT biasing and small-signal amplifiers Ch. 5–6, ADC architectures Ch. 17); C. Kittel, Introduction to Solid State Physics, 8th ed. (crystal structure and packing fraction Ch. 1, free-electron/semiconductor carrier statistics Ch. 8).
Given. $V_{ref}=3.2\,\text{V}$ for all three converters. Figure P6a: a 5-bit flash converter — a $32R$ resistor ladder (end taps $R/2$) sets 31 comparator thresholds $V_{rk}=k\cdot V_{ref}/32$, feeding a priority encoder and clocked latch. Figure P6b: a dual-slope (integrating) converter — switch $S_1$ selects $V_A$ or $+V_{ref}$ into an $R$–$C$ integrator, a comparator and control logic drive a 5-bit counter. Figure P6c: a charge-redistribution (capacitive SAR) converter — a binary-weighted capacitor array $C,\,C/2,\,C/4,\,C/8,\,C/16$ plus a terminating cap $C/16$, switched between $V_A$/$V_{ref}$/ground, compared against 0 V.
Find. (a)–(c) essay; (d) 5-bit code for $V_A=2.18\,\text{V}$; (e) conversion time for $V_A=-2.4\,\text{V}$; (f) full-scale voltage of the SAR array.
Figure P6a — flash (parallel) ADC: a resistor ladder sets 31 comparator thresholds spaced $V_{ref}/32$ apart; a priority encoder converts the thermometer code to binary, latched on the clock.
Figure P6b — dual-slope (integrating) ADC: the input is integrated for a fixed count, then de-integrated against $+V_{ref}$ while a 5-bit counter times the return to zero.
Figure P6c — charge-redistribution (capacitive SAR) ADC: a binary-weighted capacitor array plus a terminating cap $C/16$, compared against ground.
Approach. (a)–(c) identify each architecture from its block diagram and recall its standard trade-off; (d) compare $V_A$ against the ladder's $V_{ref}/32$ steps and encode the highest tripped comparator; (e) the dual-slope conversion time is a fixed integrate period plus a de-integrate period proportional to $|V_A|/V_{ref}$; (f) apply charge conservation on the SAR array's floating top plate.
Parts (b)/(c) — one advantage/disadvantage each.
Flash: advantage — fastest possible architecture, converts in a single clock cycle (all comparators fire in parallel); disadvantage — needs $2^n-1$ comparators, so area/power grow exponentially with resolution $n$.
Dual-slope: advantage — excellent accuracy and noise/interference rejection (integrating over a fixed period averages out noise, and the result is independent of the integrator's own $R$, $C$ and clock-frequency tolerances since they cancel between the integrate and de-integrate phases); disadvantage — slow, needing many clock cycles per conversion (unsuitable for high-speed sampling).
Charge-redistribution SAR: advantage — needs only $n$ clock cycles and no resistor ladder (capacitor ratios are easier to match precisely in a CMOS process than resistor ratios); disadvantage — sensitive to parasitic/stray capacitance on the switched array and comparator offset, and still an order of magnitude slower than flash.
Part (d) — flash 5-bit code. With end taps $R/2$, the ladder divides $V_{ref}$ into exactly 32 equal steps of $V_{ref}/32=3.2/32=0.1\,\text{V}$, with threshold $k$ at $V_{rk}=k(0.1\,\text{V})$. $V_A=2.18\,\text{V}$ exceeds $V_{r1}\ldots V_{r21}=2.1\,\text{V}$ but not $V_{r22}=2.2\,\text{V}$, so comparators 1–21 trip and the priority encoder reports the highest active input, 21:
$$\boxed{21_{10}=10101_2}$$
Part (e) — dual-slope conversion time. The fixed integrate phase runs for the full count of the 5-bit counter: $T_1=2^5\times(1/f)=32\,\mu\text{s}$, reaching an integrator output $|V_1|\propto|V_A|T_1/RC$. The de-integrate phase (against $+V_{ref}$) returns to zero in a time proportional to the ratio of the two slopes:
$$T_2=\frac{|V_A|}{V_{ref}}T_1=\frac{2.4}{3.2}(32\,\mu\text{s})=24\,\mu\text{s}$$
$$\text{Total conversion time}=T_1+T_2=32+24=\boxed{56\ \mu\text{s}}$$
Part (f) — SAR full-scale voltage. Just before the top plate floats, $V_o=0$ and every bottom plate sits at 0 V, so total charge on the array is zero. At full scale every binary-weighted plate ($C+C/2+C/4+C/8+C/16=\tfrac{31}{16}C$) switches to $V_{ref}$ while the terminating cap $C_T=C/16$ stays grounded; charge conservation on the now-floating top-plate node ($C_{\text{tot}}=2C$) gives
$$\tfrac{31}{16}C\,(V_{o}-V_{ref})+\tfrac{1}{16}C\,V_{o}=0\ \Rightarrow\ V_o=\frac{31}{32}V_{ref}=\frac{31}{32}(3.2)=\boxed{3.10\ \text{V}}$$
