19-Soft-A4 Real-Time Systems · May 2013
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
National Exams — May 2013 — 04-Soft-A4 Real-Time Systems. Three-hour, closed-book exam (Casio or Sharp approved calculators only). Format: six questions of equal value (20% each); any five constitute a complete paper and only the first five as they appear in the answer book are marked. All six are solved below for completeness. Where a doubt exists as to interpretation, the candidate is expected to state assumptions — engineering assumptions used below are flagged in check callouts.
Reference texts: Jane W. S. Liu, Real-Time Systems (Prentice Hall, 2000) — task models, timing requirements, FCFS and EDF scheduling; Giorgio C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications (Springer, 3rd ed.) — preemptive dynamic-priority scheduling and the optimality of EDF; Hermann Kopetz, Real-Time Systems: Design Principles for Distributed Embedded Applications (Springer, 2nd ed.) — distributed real-time control, network-induced delay and time-triggered protocols; Katsuhiko Ogata, Modern Control Engineering (Pearson, 5th ed.) — frequency-domain stability, phase margin and delay margin; Ian Sommerville, Software Engineering (Pearson, 10th ed.) — general software-engineering process context.
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Part (1) — a protocol matching the constant-delay model. A time-triggered, TDMA-based network protocol (e.g. TTP, or a TDMA/synchronous real-time Ethernet variant such as TTEthernet) fits the "constant delay" assumption directly: every node is assigned a fixed transmission slot in a repeating schedule known in advance, so a message from the sensor always occupies the same slot relative to the schedule epoch and therefore always experiences the same, bounded, deterministic latency to the controller. This is in contrast to an event-triggered, contention-based protocol (plain CSMA/CD Ethernet, or CAN under heavy bus load) where messages queue behind unpredictable traffic and the delay varies (jitter), which the zero-delay control design in Part (3) does not account for.
Part (2) — effect of excessive delay on closed-loop performance. A network delay behaves, in the frequency domain, as a pure transport lag: it adds no attenuation but contributes phase lag that grows linearly with frequency ($\angle = -\omega\tau$). As $t_{sc}+t_{ca}$ grows, this extra phase lag erodes the phase margin the controller was designed with (Part 3's $45^{\circ}$), so the closed loop first shows increased overshoot and slower, more oscillatory settling, then approaches the stability boundary, and beyond the delay margin computed below becomes unstable (sustained or growing oscillation) even though the controller itself was never redesigned. Excessive delay can also desynchronize sampled measurements from the actuator command they were meant to correct, compounding the effective lag beyond the raw network delay alone.
Part (3) — maximum tolerable network delay.
Given. Phase margin of the zero-delay design, $\varphi = 45^{\circ}$; gain-crossover frequency, $\omega_c = 3.5\ \text{rad/s}$.
Find. Maximum total network delay $t_{sc}+t_{ca}$ before the closed loop becomes unstable.
Approach. A pure delay $\tau$ has frequency response $e^{-j\omega\tau}$: unity magnitude (it does not change the gain-crossover frequency) but phase $-\omega\tau$ (radians). The phase margin $\varphi$ is, by definition, exactly how much additional phase lag the loop can absorb at its own crossover frequency $\omega_c$ before the open-loop phase reaches the $-180^{\circ}$ instability threshold; setting the delay-induced lag at $\omega_c$ equal to that margin gives the critical (maximum tolerable) delay.
| Quantity | Result |
|---|---|
| Phase margin, radians | 0.7854 rad (45°) |
| Maximum total network delay, $t_{sc}+t_{ca}$ | ≈ 0.224 s (224 ms) |