19-Soft-A4 Real-Time Systems · May 2015
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
National Exams — May 2015 — 04-Soft-A4 Real-Time Systems. Three-hour, closed-book exam (Casio or Sharp approved calculators only). Format: six questions of equal value (20% each); any five constitute a complete paper and only the first five as they appear in the answer book are marked. All six are solved below for completeness. Where a doubt exists as to interpretation, the candidate is expected to state assumptions — engineering assumptions used below are flagged in check callouts.
Reference texts: Jane W. S. Liu, Real-Time Systems (Prentice Hall, 2000) — task models, timing requirements, FCFS and EDF scheduling; Giorgio C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications (Springer, 3rd ed.) — preemptive dynamic-priority scheduling and the optimality of EDF; Hermann Kopetz, Real-Time Systems: Design Principles for Distributed Embedded Applications (Springer, 2nd ed.) — distributed real-time control, network-induced delay and time-triggered protocols; Katsuhiko Ogata, Modern Control Engineering (Pearson, 5th ed.) — frequency-domain stability, phase margin and delay margin; Ian Sommerville, Software Engineering (Pearson, 10th ed.) — general software-engineering process context.
Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.
Part (1) — a network protocol fitting the constant-delay model. A time-triggered protocol (TTP) / TDMA-based fieldbus — e.g. TTP/C, FlexRay in its static (time-triggered) segment, or a switched Ethernet network running a deterministic scheduling layer such as Time-Sensitive Networking (TSN) — fits the constant-delay assumption, because every node is assigned a fixed, pre-computed transmission slot within a repeating communication cycle known in advance to the whole network. Since each message always occupies the same slot relative to the cycle start, the end-to-end transport delay for a given sensor-to-controller or controller-to-actuator message is the same on every cycle (up to clock-sync jitter, which is itself tightly bounded) — exactly the constant, deterministic τsc/τca the problem assumes. (Contrast this with CSMA/CD Ethernet or CAN under contention, where message delay is load-dependent and only probabilistically bounded — a poor fit for the constant-delay model.)
Part (2) — effect of excessive delay on closed-loop performance. In frequency-domain terms, a pure transport delay τ in a feedback loop contributes phase lag −ωτ (radians) that grows linearly with frequency, while leaving the magnitude response unchanged. This erodes the loop's phase margin at the (unchanged) gain-crossover frequency without warning the designer via any gain-margin symptom — the loop looks fine on a Bode magnitude plot but is quietly losing its stability cushion. As delay increases: transient response first becomes more oscillatory and slower to settle (reduced effective phase margin (part 3) increases overshoot and ringing); pushed further, the loop's damping approaches zero and the system rings persistently; and beyond the critical delay found in part (3), the phase margin is consumed entirely and the closed loop becomes unstable — sustained or growing oscillation, not merely sluggish tracking. Because both τsc and τca add directly (their phase contributions sum), the network is effectively inserted as extra, uncompensated lag in a loop that was tuned assuming it did not exist.
Part (3) — maximum tolerable total network delay. A constant time delay τ has frequency response e^{-jωτ}: unity magnitude at every frequency, and phase −ωτ (radians) that grows linearly with ω. The loop was designed with phase margin φm = 45° at crossover ωc = 3.5 rad/s assuming zero delay; the network delay eats directly into that margin at the crossover frequency (magnitude is unaffected by the delay, so the crossover frequency itself does not shift to first order). The loop remains stable as long as the delay-induced phase lag at crossover does not exceed the available margin:
$$\phi_m \ge \omega_c\,(\tau_{sc}+\tau_{ca})$$
Solving for the maximum total delay,
$$\boxed{(\tau_{sc}+\tau_{ca})_{\max} = \frac{\phi_m}{\omega_c}}$$
Substituting the given values (with φm converted to radians):
$$\phi_m = 45^{\circ} = \frac{\pi}{4}\ \text{rad} = 0.7854\ \text{rad}$$
$$(\tau_{sc}+\tau_{ca})_{\max} = \frac{0.7854}{3.5} = 0.2244\ \text{s} \approx \boxed{224\ \text{ms}}$$
Any total round-trip network delay beyond ≈224 ms consumes the entire 45° design margin at the crossover frequency and drives the closed loop unstable.
| Quantity | Value |
|---|---|
| Suitable protocol class | Time-triggered / TDMA (e.g. TTP, FlexRay static segment, TSN Ethernet) |
| Phase margin, φm | 45° = 0.7854 rad |
| Crossover frequency, ωc | 3.5 rad/s |
| Max. total network delay, (τsc+τca)max | 0.2244 s ≈ 224 ms |