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04-BS-8: May 2013

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Gate-Level Circuit Analysis, NAND Synthesis and PLD Implementation
  2. Question 2 Multi-Output Karnaugh-Map Minimization with Shared Logic
  3. Question 3 Two's-Complement Representation and an 8-Bit Subtractor
  4. Question 4 JK-from-D Flip-Flop Conversion and a 4-Bit Barrel Shifter
  5. Question 5 Serial Parity Generator and Checker

Start with Question 1 →

National Exams — May 2013 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, PAL/PLA/FPGA architectures, flip-flop conversion, sequential design, arithmetic circuits; Floyd, Digital Fundamentals (11th ed., Pearson) — multiplexers, shift registers, parity generation/checking.