Question 5 of 5: Serial Parity Generator and Checker

Question 5: Serial Parity Generator and Checker (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. A serial data line $D_x$ delivering 5 data bits one per clock edge; a control input EO (EO$=1\Rightarrow$ generate even parity, EO$=0\Rightarrow$ generate odd parity); the definitions of even/odd parity as stated above (Figure Q5 shows the generator only as a black box with inputs $D_x$, EO, Clk and output Parity Bit).

Find. (a) A state diagram and a complete D flip-flop sequential circuit generating the correct parity bit after 5 bits; (b) the minimum modification that turns the generator into a checker for an incoming 5-bit datum plus its appended parity bit.

Approach. Track only the running XOR of the bits seen so far as the machine's state — this needs just 2 states regardless of word length — then select even or odd polarity with an XNOR against EO (an XNOR reproduces its first input when the second is 1, and the complement when the second is 0, matching the given EO convention exactly), gated by a small bit counter that marks the end of each 5-bit frame.

1. Define the state machine. Let the state be $P$, the XOR of every $D_x$ bit clocked in so far. There are exactly two states: $S_0$ ($P=0$, an even number of 1's seen) and $S_1$ ($P=1$, an odd number of 1's seen). On $D_x=0$ the state is unchanged; on $D_x=1$ the state toggles ($S_0\leftrightarrow S_1$). The machine resets to $S_0$ before each new 5-bit frame.

2. Realize the state machine with one D flip-flop. Feeding $D=Q\oplus D_x$ into a D-FF and clocking it once per incoming bit implements exactly the transition table above; after 5 clock edges, $Q=P=D_{x1}\oplus D_{x2}\oplus D_{x3}\oplus D_{x4}\oplus D_{x5}$, which is by construction the correct even-scheme parity bit for the 5 data bits.
3. Select even or odd parity from $P$ and EO. The output is $$\text{Parity Bit} = \overline{P \oplus \text{EO}} \quad (P \text{ XNOR EO}),$$ which equals $P$ when EO$=1$ (even parity, as required) and $P'$ when EO$=0$ (odd parity, as required), in every case making the total 1's count (5 data bits $+$ parity bit) even when EO$=1$ and odd when EO$=0$.
4. Frame the 5-bit word with a bit counter. A MOD-5 counter (3 D flip-flops, since $\lceil\log_2 5\rceil=3$) clocked alongside the parity flip-flop counts the incoming bits and asserts a "Done" pulse on the 5th clock; ANDing Done with the XNOR output releases a valid Parity Bit exactly once per frame, after which both the counter and the parity flip-flop are cleared for the next 5-bit word.

5. Part (b) — modify for checking. The incoming stream now carries 6 bits per frame (5 data bits plus the already-appended parity bit), so the bit counter is widened from MOD-5 to MOD-6. For an error-free frame, the running XOR of all 6 received bits equals 0 when the sender used even parity (EO$=1$) and equals 1 when the sender used odd parity (EO$=0$) — i.e. the expected 6-bit XOR is $\overline{\text{EO}}$. The output logic is therefore changed from an XNOR-based generator to a plain XOR comparison, $$\text{Error} = \big(D_{x1}\oplus\cdots\oplus D_{x6}\big) \oplus \overline{\text{EO}},$$ gated by the MOD-6 counter's "Done" pulse; Error$=1$ flags a single-bit (or any odd number of bit) error in the received 6-bit codeword. Verified for all 32 data patterns, both EO values, and an error-free vs. single-bit-flipped received parity bit.