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04-BS-8 · May 2013

Question 3 of 5: Two's-Complement Representation and an 8-Bit Subtractor

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

Notes on this paper

National Exams — May 2013 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, PAL/PLA/FPGA architectures, flip-flop conversion, sequential design, arithmetic circuits; Floyd, Digital Fundamentals (11th ed., Pearson) — multiplexers, shift registers, parity generation/checking.

Question 3: Two's-Complement Representation and an 8-Bit Subtractor (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Decimal magnitude 139, to be stored as a 10-bit 2's complement number; two 8-bit operands $A,B$ to be subtracted using cascaded 4-bit parallel adder ICs (74LS283, appendix data sheet).

Find. (a) The 10-bit 2's complement bit pattern for $-139$; (b) an 8-bit $A-B$ subtractor built from 74LS283 adders.

Approach. For (a), write $+139$ in 10-bit binary, invert every bit (1's complement) and add 1. For (b), use the identity $A-B = A + \overline{B} + 1$ (2's-complement subtraction): XOR every bit of $B$ with a single SUB control line so $B$ passes through unchanged when SUB$=0$ or is bit-inverted when SUB$=1$, and tie SUB into the carry-in of the low-order adder to supply the "$+1$"; cascade two 74LS283 nibble adders for the full 8 bits.

  1. Part (a) — write $+139$ in 10-bit binary. $139 = 128+8+2+1$, so the 8-bit pattern is $10001011$; padded to 10 bits, $+139 = 0010001011_2$.
  2. Part (a) — take the 1's complement (invert every bit). $$0010001011 \;\longrightarrow\; 1101110100.$$
  3. Part (a) — add 1 to get the 2's complement. $$1101110100 + 1 = \boxed{1101110101}$$ Checked by reinterpreting $1101110101_2$ as a signed 10-bit number ($-2^9$ weight on the leading bit): the decoded value is exactly $-139$.
  4. Part (b) — condition the $B$ operand with an XOR/SUB stage. Each of the 8 bits of $B$ is XOR'd with a common SUB line: $B_i\oplus\text{SUB}=B_i$ when SUB$=0$ (straight addition) and $B_i\oplus\text{SUB}=\overline{B_i}$ when SUB$=1$ (bit-inversion, the first step of forming $-B$).
  5. Part (b) — supply the "$+1$" and cascade the two nibble adders. Tying SUB into the carry-in ($C_{in}$) of the low-order 74LS283 adds the required $+1$ exactly when SUB$=1$, completing $A+\overline{B}+1=A-B$; the low nibble's carry-out $C_4$ feeds the high-order 74LS283's carry-in, so the two 4-bit adders behave as one ripple-carry 8-bit adder/subtractor.
  6. Part (b) — interpret the result. With SUB$=1$: if $A\ge B$ the final carry-out is 1 (no borrow) and the sum output $S[7{:}0]$ is the true-binary result $A-B$; if $A
A[7:4]A[3:0]B[7:4]B[3:0]SUBXORXORB[7:4]⊕SUBB[3:0]⊕SUB74LS283(low nibble, bits 3-0)74LS283(high nibble, bits 7-4)A[7:4]B[7:4]⊕SUBA[3:0]Cin=SUBC4S[3:0]S[7:4]Cout / borrow-out
8-bit 2's-complement subtractor: an XOR gate per $B$ bit (controlled by SUB) conditions the subtrahend, and SUB also supplies $C_{in}$ to the low-nibble 74LS283; the carry $C_4$ ripples into the high-nibble 74LS283.
Check
SUB$=1$ selects subtraction and SUB$=0$ selects ordinary addition — the paper does not name the control line, so this polarity is an engineering choice made explicit here; reversing it only swaps which logic level means "subtract."
QuantityResult
$+139$, 10-bit binary$0010001011_2$
$-139$, 10-bit 2's complement$\boxed{1101110101_2}$
8-bit subtractor architecture8 XOR gates on $B$ (control = SUB) + SUB into $C_{in}$ of the low 74LS283 + carry-cascaded high 74LS283