Question 4 of 5: D-from-JK Conversion and a Minimum-Flip-Flop Down Counter
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — December 2014 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
Given. A JK flip-flop with characteristic equation $Q^+=J\overline Q+\overline K Q$, to be wired as a D-type; and a required 4-bit down-count sequence $15,13,11,9,7,5,3,1,15,\ldots$ (period 8, all odd values).
Find. (a) A gate/wiring scheme that makes a JK flip-flop behave as a D flip-flop; (b) a minimum-flip-flop, minimum-gate circuit that generates the given down-count sequence.
Approach. For (a), substitute $J=D,\ K=\overline D$ into the JK characteristic equation and confirm it collapses to $Q^+=D$. For (b), notice every value in the sequence is odd (so the LSB never changes and needs no flip-flop), leaving an ordinary 3-bit binary down-counter on the remaining bits, whose D-equations follow the standard "toggle when all lower bits are 0" down-counter rule.
Part (a) — tie $J=D$, $K=\overline D$. Substituting into the JK characteristic equation,
$$Q^+ = J\overline Q+\overline K Q = D\overline Q + \overline{\overline D}\,Q = D\overline Q+DQ = D(\overline Q+Q) = \boxed{D},$$
exactly the D-type characteristic equation, for both $Q=0$ and $Q=1$. One inverter (to form $\overline D$ for the $K$ input) is the only extra component needed.
Part (a): a D flip-flop from a JK flip-flop — tie $J=D$ directly and $K=\overline{D}$ through one inverter. Then $Q^+=J\overline Q+\overline K Q=D\overline Q+DQ=D$, exactly the D-type characteristic equation, for both $Q=0$ and $Q=1$.
Part (b) — recognize the trivial LSB. Every value in $15,13,11,9,7,5,3,1$ is odd, so the least-significant bit $Q_0$ of the 4-bit output is always 1 and never toggles. $Q_0$ can therefore be hard-wired straight to logic 1 (Vcc) — no flip-flop is needed for it at all, which is exactly the "minimum number of D-type flip-flops" the question asks for: 3 flip-flops suffice, not the 4 a literal reading of "4-bit counter" might suggest.
Part (b) — reduce to a 3-bit down-counter. Writing each value as $2k+1$, the sequence's $k=(n-1)/2$ values are $7,6,5,4,3,2,1,0$ — an ordinary 3-bit binary down-counter on $(Q_3,Q_2,Q_1)$, wrapping $0\to7$. A synchronous binary down-counter toggles bit $i$ exactly when every lower bit is currently 0, giving the standard D-equations
$$D_1=\overline{Q_1},\qquad D_2=Q_2\oplus\overline{Q_1},\qquad D_3=Q_3\oplus\big(\overline{Q_2}\cdot\overline{Q_1}\big),$$
verified to reproduce the full 8-state down-count for every present state (e.g. from $Q_3Q_2Q_1{=}111$ the equations give next-state $110$, i.e. $15\to13$, matching the given sequence).
Part (b): only 3 D flip-flops are used — the sequence 15,13,...,1 is always odd, so $Q_0$ never changes and is tied straight to logic 1 (saving the 4th flip-flop the naive design would use). $Q_3Q_2Q_1$ form an ordinary 3-bit synchronous binary down-counter: $D_1=\overline{Q_1}$, $D_2=Q_2\oplus\overline{Q_1}$, $D_3=Q_3\oplus(\overline{Q_2}\cdot\overline{Q_1})$.
Check
Hard-wiring $Q_0$ to logic 1 assumes the 4-bit output only ever needs to be read as $Q_3Q_2Q_1Q_0$ (never independently loaded/cleared) — a reasonable reading of "design ... a counter" with no load/reset requirement stated.
