Question 5 of 5: 7-Bit Parity Generator and Checker Modification
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — December 2014 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
Given. 7 parallel data bits $D_0,\ldots,D_6$; a control input $EP$ selecting even ($EP{=}1$) or odd ($EP{=}0$) parity; for part (b), an additional incoming parity bit $P_{in}$ received along with the 7 data bits.
Find. (a) A minimum-gate circuit generating the correct parity bit for either mode selected by $EP$; (b) a modification of that same circuit that checks, rather than generates, parity.
Approach. Build the "odd function" $P=D_0\oplus D_1\oplus\cdots\oplus D_6$ (an XOR tree), which is 1 exactly when the data has an odd number of 1s; show that $P$ itself is the correct even-parity bit and $\overline P$ the correct odd-parity bit, then combine with $EP$ through one more XOR/XNOR stage so a single control line selects between them. For (b), extend the same tree to include $P_{in}$ and reinterpret the final stage's output as an error flag.
Part (a) — build the odd-function $P$ and confirm the parity claim. With $P=D_0\oplus D_1\oplus\cdots\oplus D_6$ (6 cascaded 2-input XOR gates, $P=1$ iff the data has an odd count of 1s): if the data has an odd number of 1s, appending the bit $P{=}1$ makes the 8-bit total even; if the data has an even number of 1s, $P{=}0$ and appending it leaves the total even as well. So $P$ itself is always the correct EVEN-parity bit, and by the same argument $\overline P$ is always the correct ODD-parity bit.
Part (a) — select the mode with $EP$. The output must equal $P$ when $EP{=}1$ and $\overline P$ when $EP{=}0$; that selection is exactly an XNOR of $P$ and $EP$ (verify: $EP{=}1\Rightarrow P\;\text{XNOR}\;1=P$; $EP{=}0\Rightarrow P\;\text{XNOR}\;0=\overline P$), so
$$\text{output} = \boxed{P \;\text{XNOR}\; EP}.$$
Total gate count: 6 XOR (tree) $+$ 1 XNOR (mode select) $=$ 7 two-input gates, verified against all $2^7\times2=256$ data/$EP$ combinations.
Part (a) (solid): a 6-XOR tree combines $D_0..D_6$ into $P$ (odd-function of the data), and a final XNOR with $EP$ selects even ($EP{=}1\Rightarrow$output$=P$) or odd ($EP{=}0\Rightarrow$output$=\overline P$) parity. Part (b) (dashed): folding the incoming parity bit $P_{in}$ into the tree (one extra XOR, 7 total) forms the full 8-bit syndrome $S$; the same final XNOR stage now reads as an ERROR flag ($S\;\text{XNOR}\;EP=1$ signals a parity mismatch) — the generator becomes a checker by reinterpreting its output, with one added XOR gate.
Part (b) — fold $P_{in}$ into the tree. Extend the XOR tree by one more stage, $S=P\oplus P_{in}$ (7 XOR gates total, combining all 8 received bits), so $S$ is the "odd function" of the received 8-bit word. If the word was correctly encoded for the selected mode, $S$ must equal $EP$ exactly — a correctly even-parity-encoded word has an even total of 1s, so its 8-bit odd-function $S=0$, matching $EP{=}1$'s complement convention (and symmetrically for odd parity, $S=1$ matches $EP{=}0$). So a mismatch (error) is signalled by $S=EP$:
$$\text{Error} = \boxed{S \;\text{XNOR}\; EP},$$
reusing the exact same final XNOR stage from part (a), now reinterpreted: one extra XOR gate (8 gates total) turns the generator into a checker.
Check
"Error" here means the received word is inconsistent with the selected parity mode; a real single-bit transmission error is guaranteed to be caught (parity always changes), but this scheme (like any single-parity-bit code) cannot detect an even number of simultaneous bit errors.
