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04-BS-8: May 2015

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Serial Sequence Detector (11010) with JK Flip-Flops
  2. Question 2 ROM vs. FPGA, PAL16L8 and Decoder Implementation
  3. Question 3 Short-Answer Justify Questions
  4. Question 4 D Flip-Flop from SR Flip-Flop; Minimum-Hardware Down-Counter
  5. Question 5 Combinational Multiplier (3-bit × Constant 3)

Start with Question 1 →

National Exams — May 2015 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.

Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, PAL/PLA/FPGA architectures, flip-flop conversion, sequential design, arithmetic circuits; Floyd, Digital Fundamentals (11th ed., Pearson) — decoders, number systems, flip-flop characteristic tables, counters.