D Flip-Flop from SR Flip-Flop; Minimum-Hardware Down-Counter: 04-BS-8, May 2015, Q4

Question 4: D Flip-Flop from SR Flip-Flop; Minimum-Hardware Down-Counter (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. An SR flip-flop and basic gates are available for part (a); part (b) needs a 4-bit counter that cycles $14\to12\to10\to8\to6\to4\to2\to0\to14\to\dots$ using the fewest D flip-flops and gates.

Find. (a) A gate-level construction of a clocked D flip-flop from an SR flip-flop; (b) the minimum-hardware state diagram, state table, next-state equations and counter realizing the given 4-bit down-count sequence.

Approach. For (a), gate $D$ and its complement $\overline{D}$ with CLK into the SR latch's $S,R$ inputs so $S,R$ are never simultaneously asserted. For (b), notice every value in the sequence is even, so the LSB never needs to be stored at all — the remaining 3 bits are then just an ordinary 3-bit binary down-counter, minimized by K-map with no unused states (all 8 codes are visited).

Part (a) — D flip-flop from an SR latch. Tie $S = D\cdot\text{CLK}$ and $R = \overline{D}\cdot\text{CLK}$ (one inverter to form $\overline{D}$, two AND gates to gate both with the clock). Because $S$ and $R$ are always complementary whenever CLK is asserted, the forbidden $S{=}R{=}1$ SR state can never occur, and the latch's next output is forced to exactly $D$: $D{=}1\Rightarrow(S,R){=}(1,0)\Rightarrow Q^+{=}1$; $D{=}0\Rightarrow(S,R){=}(0,1)\Rightarrow Q^+{=}0$.

Part (a): D flip-flop built from an SR latch — $S=D\cdot\text{CLK}$, $R=\overline{D}\cdot\text{CLK}$ (1 inverter + 2 AND gates) guarantee $S,R$ are never both asserted, forcing $Q^+=D$ on every clock.

Part (b) — recognize $Q_0$ never needs storage. Every value in $14,12,10,\dots,0$ is even, so the 4-bit output's LSB $Q_0$ is permanently 0 — it can simply be tied to ground, needing no flip-flop at all. The remaining bits $Q_3Q_2Q_1$ (dividing every output value by 2) must cycle $7,6,5,4,3,2,1,0,7,\dots$: an ordinary 3-bit binary down-counter, with all 8 codes visited (no don't-cares).
Part (b) — state table and minimized next-state (=D, for D flip-flops) equations. Tabulating $Q_3Q_2Q_1\to(Q_3Q_2Q_1){-}1 \bmod 8$ for all 8 states and K-map-minimizing each bit (since a D flip-flop's excitation input IS simply its next-state value, no separate excitation table is needed) gives $$D_3 = Q_1Q_3+Q_2Q_3+\overline{Q_1}\,\overline{Q_2}\,\overline{Q_3}, \qquad D_2 = Q_1Q_2+\overline{Q_1}\,\overline{Q_2}, \qquad \boxed{D_1 = \overline{Q_1}}$$

Part (b): minimum-hardware down-counter — only 3 D flip-flops are needed (for $Q_3,Q_2,Q_1$), sharing one CLK; $Q_0$ is grounded rather than stored, since every output value in 14,12,...,0 is even.

Check

Recognizing that $Q_0{\equiv}0$ removes an entire flip-flop plus its next-state gating is the intended "minimum number of D-type flip-flops" reading of the question — a naive 4-bit design would use 4 flip-flops and a 4th (trivial, always-0) next-state equation for no benefit.

Quantity	Result
(a) D-FF from SR	$S=D\cdot\text{CLK}$, $R=\overline{D}\cdot\text{CLK}$ — 1 inverter + 2 AND gates + 1 SR latch
(b) Next-state equations	$D_3=Q_1Q_3+Q_2Q_3+\overline{Q_1}\,\overline{Q_2}\,\overline{Q_3}$; $D_2=Q_1Q_2+\overline{Q_1}\,\overline{Q_2}$; $D_1=\overline{Q_1}$
(b) Hardware	3 D flip-flops + gates for $D_3,D_2$ ($D_1$ is a direct $\overline{Q_1}$ feedback); $Q_0$ tied to 0
(b) Output sequence	14, 12, 10, 8, 6, 4, 2, 0, 14, … (confirmed for all 8 states)

Concept & Theory

Topic. Flip-flop conversion (SR→D) and minimum-hardware synchronous counter design.

Key relations. SR latch behaviour $Q^+=S+\overline{R}Q$ (with $S,R$ never both 1); D flip-flop excitation is trivial, $D=Q^+$ directly (no excitation table needed, unlike JK/T); binary down-count recurrence $V^+=(V-1)\bmod 2^n$.

Why this works. Gating $S=D\cdot\text{CLK}$ and $R=\overline{D}\cdot\text{CLK}$ guarantees the SR latch's forbidden state never arises, collapsing its behaviour to "store whatever $D$ was at the clock edge" — the defining behaviour of a D flip-flop. In part (b), since a D flip-flop's next-state input is just the desired next output, minimum hardware follows immediately from minimizing the state encoding itself (dropping the always-0 LSB) before ever drawing a single gate.

Common pitfall. Building a full 4-bit counter (4 flip-flops, with $D_0$ trivially 0) instead of noticing the LSB can be dropped entirely; or, in part (a), gating only $S$ with the clock and leaving $R=\overline{D}$ un-gated, which would violate the SR latch's timing and defeat synchronous operation.

Source. Mano & Ciletti, Digital Design, Ch. 5 (flip-flop conversion, D flip-flop) & Ch. 6 (synchronous counter design).

Question 4 of 5: D Flip-Flop from SR Flip-Flop; Minimum-Hardware Down-Counter

Question 4: D Flip-Flop from SR Flip-Flop; Minimum-Hardware Down-Counter (25 marks)