Question 5 of 5: Combinational Multiplier (3-bit × Constant 3)
Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
National Exams — May 2015 — 04-BS-8 Digital Logic Circuits. Three-hour, closed-book exam (Casio or Sharp approved calculator only; one hand-written 8.5"×11" aid sheet permitted). Format: five questions offered, each worth 25 marks (100 total); any four constitute a complete paper and only the first four appearing in the answer book are marked. All five are solved below for completeness.
Reference texts: Mano & Ciletti, Digital Design (6th ed., Pearson) — Boolean minimization, PAL/PLA/FPGA architectures, flip-flop conversion, sequential design, arithmetic circuits; Floyd, Digital Fundamentals (11th ed., Pearson) — decoders, number systems, flip-flop characteristic tables, counters.
Given. A 3-bit multiplicand $A_2A_1A_0$ (values 0–7) is multiplied by the fixed constant $3_{10}$; the multiplier is a hardwired constant, not a separate signal.
Find. (a) $m,n,r$; (b) the full input/output truth table; (c)/(d) minimized Boolean expressions for every result bit and a minimum-NAND-gate implementation.
Approach. Because the multiplier is a fixed constant rather than a variable input, it contributes zero input lines — the whole circuit is just "$3\times A$" as a function of $A_2A_1A_0$ alone. Tabulate $3A$ for $A=0..7$, minimize each of the 5 result bits by K-map, then convert the two-level AND-OR realization to NAND-NAND gates (assuming both true and complemented literals are available, as in the PAL-array problems above).
Part (a) — count $m,n,r$. The multiplicand needs $\boxed{m=3}$ input lines ($A_2A_1A_0$, values 0–7). The multiplier is the fixed constant 3 — it is built into the logic, not applied as a signal, so $\boxed{n=0}$ input lines. The largest possible product is $7\times3=21=(10101)_2$, which needs 5 bits, so $\boxed{r=5}$ output lines (a 4-bit result would max out at 15, too small for 21).
$A_2A_1A_0$
$A$ (dec)
$R_4R_3R_2R_1R_0$
$3A$ (dec)
000
0
00000
0
001
1
00011
3
010
2
00110
6
011
3
01001
9
100
4
01100
12
101
5
01111
15
110
6
10010
18
111
7
10101
21
Part (b) — truth table. The full 8-row table above lists every input combination $A_2A_1A_0$ and the corresponding 5-bit product $R_4R_3R_2R_1R_0=3A$.
Part (c) — Boolean-algebra shortcut. Since $3A=2A+A=(A{\ll}1)+A$, the result is simply $A$ added to itself shifted one place — a 3-bit binary adder with one operand pre-shifted would also realize this, but a direct minterm-by-minterm K-map minimization (below) gives a smaller two-level circuit than instantiating a full adder.
Part (d) — K-map minimization of every output bit. Grouping each $R_i$'s 1-cells on a 3-variable K-map over $(A_2,A_1,A_0)$ gives
$$R_0 = A_0, \qquad R_1 = A_0\overline{A_1}+A_1\overline{A_0}, \qquad R_2 = A_0A_2+A_2\overline{A_1}+A_1\overline{A_0}\,\overline{A_2},$$
$$R_3 = A_2\overline{A_1}+A_0A_1\overline{A_2}, \qquad \boxed{R_4 = A_1A_2}$$
Part (d): NAND-only realization of $R_4=A_1A_2$, the simplest output bit — a NAND gate on $A_1,A_2$ followed by a NAND wired as an inverter restores the true AND. Every other output bit converts the same way: replace each AND-OR two-level SOP with a NAND-NAND network of identical topology (De Morgan's theorem guarantees this preserves the function).
Check
$m,n,r$ in part (a) assumes the multiplier "3" is realized as fixed wiring (the natural reading of "multiply by a constant" and of Figure Q5 labelling it separately from the multiplicand input) rather than as a second 3-bit input bus, which is what makes $n=0$ the intended answer rather than $n=3$.
Quantity
Result
(a) $m,n,r$
$m=3$ (multiplicand), $n=0$ (fixed multiplier constant), $r=5$ (result, since $7\times3=21$)
(b) Truth table
8 rows, $A=0..7\to 3A=0,3,6,9,12,15,18,21$ (see table above)
