Question 3 of 5: Flip-Flop Conversion, Boolean Evaluation, Characteristic Table, 4-1 MUX

Question 3: Flip-Flop Conversion, Boolean Evaluation, Characteristic Table, 4-1 MUX (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Part (a) — D flip-flop from a JK flip-flop. A JK flip-flop's characteristic equation is Q⁺ = J·Q′ + K′·Q. Setting J=D and K=D′ forces Q⁺ = D·Q′ + D·Q = D (using D+D=D and factoring), i.e. Q⁺=D regardless of the present state — exactly the D flip-flop's own characteristic equation. Only one gate is needed: an inverter feeding K from D, with J tied directly to D.

Part (b). With A=1, B=0, C=1: $A \oplus B = 1\oplus 0 = 1$, so $\overline{(A\oplus B)} = 0$. $A\cdot C = 1\cdot 1 = 1$. $$X = 0 + 1 = \boxed{1}$$

Part (c) — identify the flip-flop. Reading the table as a characteristic table: (A,B)=(0,0) holds state, (1,0)→0, (0,1)→1, and (1,1) is explicitly indeterminate. That last row is the tell: a JK flip-flop resolves (1,1) to a defined toggle, a D flip-flop has no such row at all, and a T flip-flop has only one control input — only the SR (Set-Reset) flip-flop leaves the “both asserted” combination explicitly forbidden/undefined. Matching roles: A behaves as Reset (A=1→Q⁺=0) and B as Set (B=1→Q⁺=1), giving the standard SR characteristic equation $$\boxed{Q^+ = B + \bar{A}\,Q_n} \quad (A=R,\ B=S)$$.

Part (d) — 4-to-1 MUX, minimum AND/OR count. The direct sum-of-products realization is $$X = A\bar{S_1}\bar{S_0} + B\bar{S_1}S_0 + CS_1\bar{S_0} + DS_1S_0$$ one 3-input AND gate per data line (gating it by the unique minterm of S1,S0 that selects it), summed by one OR gate. No smaller gate count is possible for a 2-level realization of a 4-way single-line select: each of the 4 mutually-exclusive selection conditions needs its own product term (dropping any AND gate would leave some (S1,S0) combination unable to route its data bit through), and one OR gate is the minimum to sum 4 terms into a single output. $$\boxed{4\text{ AND gates (3-input)} + 1\text{ OR gate (4-input)} = 5\text{ gates}}$$ (plus 2 inverters, outside the AND/OR count, to supply S1′ and S0′) — verified against all 64 (A,B,C,D,S1,S0) combinations.