Two-Flip-Flop Counter — Synchronicity, State Detection, Timing: 04-BS-8, May 2017, Q4

Question 4: Two-Flip-Flop Counter — Synchronicity, State Detection, Timing (25 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. D1 = Q2, D2 = Q1′ (both flip-flops driven from the same Clock line), Z = Q1·Q2, both flip-flops reset to (Q1,Q2)=(0,0), clock = 10 MHz, flip-flop propagation delay 10 ns, AND-gate propagation delay 5 ns.

Find. (a) synchronous or not, with justification; (b) which (Q1,Q2) state Z flags; (c) the Q1, Q2, Z waveforms over a full cycle.

Approach. Build the one-step-ahead state table from D1=Q2, D2=Q1′, walk it from the reset state to find the repeating cycle, then lay the timing diagram out against the 100 ns clock period using the two stated propagation delays.

Part (a) — synchronous? Both D flip-flops are driven by the same Clock signal, and neither flip-flop's output clocks the other (Q1 and Q2 feed only D inputs, never CLK inputs). Every state change in the circuit therefore happens on the same clock edge, simultaneously — the defining property of a synchronous sequential circuit (as opposed to a ripple/asynchronous design, where one flip-flop's output clocks the next). $$\boxed{\text{Yes -- synchronous (single shared clock, no FF-to-FF clocking)}}$$
Part (b) — state table and detected state. With D1=Q2 and D2=Q1′, the next state (Q1⁺,Q2⁺) = (Q2, Q1′). Starting from (0,0): $$ (0,0)\to(0,1)\to(1,1)\to(1,0)\to(0,0)\to\cdots $$ a repeating 4-state cycle (this is a standard 2-bit Gray-code sequence: 00, 01, 11, 10). Z=Q1·Q2 is 1 on exactly one of the four states. $$\boxed{\text{AND gate detects state } Q_1Q_2=11 \text{, occurring once every 4 clock cycles}}$$
Part (c) — timing. Clock period at 10 MHz is 100 ns, edges at t=0,100,200,300,400 ns. Each flip-flop's output settles 10 ns after the triggering edge (t=110, 210, 310, 410 ns), stepping through the cycle found in part (b): Q1 goes 0→1 at t=210 ns (holds through the 11 state) and 1→0 at t=410 ns; Q2 goes 0→1 at t=110 ns and 1→0 at t=310 ns. Both are simultaneously 1 only in the window [210,310) ns; the AND gate adds a further 5 ns, so $$\boxed{Z \text{ is high from } 215\text{ ns to } 315\text{ ns, once every 400 ns}}$$

Fig. Q4(c) — timing diagram, 10 MHz clock (100 ns period), 10 ns flip-flop delay, 5 ns AND-gate delay. Q1/Q2 settle 10 ns after each rising edge; Z (blue) follows 5 ns after Q1=Q2=1 is reached, high for the 210–310 ns window plus the 5 ns gate delay (215–315 ns).

Final results — Question 4
Item	Result
(a)	Yes — synchronous (one shared clock, no FF clocks another)
(b)	State Q1Q2 = 11 (once per 4-cycle Gray sequence)
(c)	Clock period 100 ns; Z high 215–315 ns each cycle

Concept & Theory

Topic: Synchronous vs. asynchronous sequential circuits; state-table derivation; propagation-delay timing diagrams.

Key relations: next-state = f(D inputs) evaluated at the present state; a synchronous circuit changes all state on one common clock edge; observable output lags the triggering edge by the sum of every delay in its path (flip-flop delay, then any combinational gate delay).

Why this works: Because D1 and D2 are combinational functions of the CURRENT Q1,Q2 (not of each other's new value), the state table can be walked one step at a time from reset to find the steady-state cycle before any timing numbers are needed.

Common pitfall: Forgetting to add the AND gate's own 5 ns on top of the flip-flops' 10 ns when timing Z — Z's edges lag the flip-flop edges, not the clock edges directly.

Source: Mano & Ciletti, Digital Design §9.1–9.2 (synchronous sequential circuit analysis, state tables); Floyd, Digital Fundamentals §on propagation delay and timing diagrams.

Question 4 of 5: Two-Flip-Flop Counter — Synchronicity, State Detection, Timing

Question 4: Two-Flip-Flop Counter — Synchronicity, State Detection, Timing (25 marks)