Question 6 of 7: CMOS Static Logic Synthesis and Sizing

Question 6: CMOS Static Logic Synthesis and Sizing (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $k_n'=100\,\mu\text{A/V}^2$, $k_p'=50\,\mu\text{A/V}^2$; $|V_t|=1\text{V}$; $V_{DD}=5\text{V}$; reference symmetric inverter $(W/L)_{n,\text{ref}}=2$, $(W/L)_{p,\text{ref}}=5$; $C_L=1\text{pF}$.

Find. Gate-level NMOS/PMOS network; per-transistor $W/L$ sizes; estimated propagation delay $t_p$.

Approach. Rewrite $F=\overline{D+A(B+C)}=\overline D\cdot(\overline A+\overline B\overline C)$ (De Morgan): the pull-down (NMOS) network directly mirrors $D+A(B+C)$ — $D$ alone in parallel with $A$ in series with $(B\parallel C)$ — and the pull-up (PMOS) network is its series/parallel dual, $D$ in series with $\big(A\parallel(B\text{-}C)\big)$. Each transistor is then sized so its own worst-case series path matches the single reference inverter's drive strength.

1. Part (a) — gate synthesis. Pull-down network (NMOS): $D$ (standalone branch) in parallel with $\big[A\text{ series }(B\parallel C)\big]$ — this conducts (pulling $F$ low) exactly when $D=1$ or $A\cdot(B+C)=1$, matching $F$'s defining OR/AND structure. Pull-up network (PMOS) is the series/parallel dual: $D$ in series with $\big[A\parallel(B\text{ series }C)\big]$ — conducting (pulling $F$ high) exactly when $\overline D\cdot(\overline A+\overline B\overline C)=1$, i.e. $F=1$. Eight transistors total (one N + one P per literal $D,A,B,C$), the standard count for a 4-literal AOI gate.
2. Part (b) — sizing. Each transistor's $W/L$ is scaled by the number of transistors in the deepest series path it personally belongs to, relative to the reference $(W/L)_{n,\text{ref}}=2$ / $(W/L)_{p,\text{ref}}=5$ single inverter:
   NMOS — $D$ (never in series, depth $1$): $W/L=1\times2=\boxed{2}$. $A,B,C$ (each in the $2$-deep $A$-$B$ or $A$-$C$ path): $W/L=2\times2=\boxed{4}$ each.
   PMOS — $A$ (worst path $D$-$A$, depth $2$): $W/L=2\times5=\boxed{10}$. $D,B,C$ (each on the $3$-deep $D$-$B$-$C$ path, the network's longest): $W/L=3\times5=\boxed{15}$ each.
3. Part (c) — propagation delay. Because the sizing in (b) was chosen specifically so every worst-case series path matches the single reference inverter's drive strength, $t_p$ is estimated directly from the reference device sizes using the saturation-current (square-law) approximation $I_{D,\text{sat}}=\tfrac{\beta}{2}(V_{DD}-V_t)^2$ with $\beta=k'(W/L)_{\text{ref}}$: $$\beta_n=k_n'(W/L)_{n,\text{ref}}=100\,\mu\times2=200\,\mu\text{A/V}^2,\quad I_{Dn,\text{sat}}=\frac{200\,\mu}{2}(5-1)^2=1.6\text{ mA}$$ $$\beta_p=k_p'(W/L)_{p,\text{ref}}=50\,\mu\times5=250\,\mu\text{A/V}^2,\quad I_{Dp,\text{sat}}=\frac{250\,\mu}{2}(5-1)^2=2.0\text{ mA}$$ $$t_{pHL}=\frac{C_L(V_{DD}/2)}{I_{Dn,\text{sat}}}=\frac{(1\text{pF})(2.5)}{1.6\text{mA}}=1.56\text{ ns},\quad t_{pLH}=\frac{(1\text{pF})(2.5)}{2.0\text{mA}}=1.25\text{ ns}$$ $$t_p=\frac{t_{pHL}+t_{pLH}}{2}=\boxed{1.41\text{ ns}}$$