Question 7 of 7: Flash-ADC Comparator Ladder and Encoder

Question 7: Flash-ADC Comparator Ladder and Encoder (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. $V_{\text{ref}}=5\text{V}$; four equal $10\text{k}\Omega$ ladder resistors (three interior taps); comparator convention (per the figure): $+$ input $=$ ladder tap, $-$ input $=V_{\text{in}}$, so the output is HIGH when the tap voltage exceeds $V_{\text{in}}$.

Find. $V_1,V_2,V_3$ in terms of $V_{\text{in}}$; $V_4,V_5$ in terms of $V_1,V_2,V_3$; comparator count for 4 output bits; resolution.

Approach. Each comparator's $+$ input sees a fixed fraction of $V_{\text{ref}}$ set by the resistor ladder; because $+$ is the ladder tap and $-$ is $V_{\text{in}}$, each output is HIGH whenever $V_{\text{in}}$ is below that comparator's own threshold, giving a descending (complemented) thermometer code as $V_{\text{in}}$ rises. The XOR gates mark transitions between adjacent thermometer bits, and the diodes (each pulled low by its $10\text{k}\Omega$) perform a logical OR of whichever transition signals feed each output rail.

1. Part (a) — comparator thresholds. The ladder taps sit at $\tfrac34,\tfrac24,\tfrac14$ of $V_{\text{ref}}$ (three interior nodes of four equal resistors): $$V_1=1\text{ if }V_{\text{in}}\lt\tfrac34V_{\text{ref}}=\boxed{3.75\text{ V}},\quad V_2=1\text{ if }V_{\text{in}}\lt\tfrac24V_{\text{ref}}=\boxed{2.50\text{ V}},\quad V_3=1\text{ if }V_{\text{in}}\lt\tfrac14V_{\text{ref}}=\boxed{1.25\text{ V}}$$ (each $=0$ otherwise). As $V_{\text{in}}$ rises through $0$–$5\text{V}$, $(V_1,V_2,V_3)$ steps $111\to110\to100\to000$ — a complemented thermometer code, since the comparator polarity is reversed from the more familiar "$+=V_{\text{in}}$" convention.
2. Part (b) — $V_4,V_5$ expressions. Let $X_1=V_1\oplus0=V_1$ (topmost XOR, tied to ground), $X_2=V_1\oplus V_2$, $X_3=V_2\oplus V_3$ (the three transition detectors). Tracing the diode-OR network as drawn, $X_1$ feeds a diode into each output rail, $X_2$ feeds $V_4$, and $X_3$ feeds $V_5$: $$V_4=X_1+X_2=V_1+(V_1\oplus V_2)=\boxed{V_1+V_2}\qquad\text{(Boolean OR; identity }A+(A\oplus B)=A+B\text{)}$$ $$V_5=X_1+X_3=\boxed{V_1+(V_2\oplus V_3)}$$ Since the code is monotonic ($V_1\ge V_2\ge V_3$ for any valid $V_{\text{in}}$), $V_4=V_1+V_2$ reduces to $V_4=V_1$, and $V_5$ reduces to the same value ($V_1$) whenever $V_1=1$, and to $0$ only when $V_1=V_2=V_3=0$ — see the check note below.
3. Part (c) — comparators for 4 bits. A flash ADC needs one comparator per quantization boundary; an $n$-bit flash converter has $2^n$ levels and therefore $2^n-1$ boundaries/comparators: $$N_{\text{comp}}=2^4-1=\boxed{15\text{ comparators}}$$
4. Part (d) — resolution. With $3$ comparators this circuit has $4$ quantization levels, i.e. an effective $2$-bit converter, and the ladder step (the smallest voltage the circuit can distinguish) is $$\Delta V=\frac{V_{\text{ref}}}{2^2}=\frac{5\text{V}}{4}=\boxed{1.25\text{ V}}$$ — exactly the ladder's own tap spacing found in part (a), as expected.