Question 1 of 6: Digital Design and VHDL Concepts

Question 1: Digital Design and VHDL Concepts (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Find. The single best answer, with reasoning, for each of the ten 2-mark sub-questions on HDL/digital-design terminology and semantics.

1.1 — Answer: C. RTL = Register Transfer Level, the abstraction at which a design is described as registers, the values that flow between them each clock, and the operations performed on those values — the level a VHDL/Verilog synthesis tool actually consumes. Neither "Relational Timing Logic" (A) nor "Relative Transfer Latches" (B) are real terms in digital design.

1.2 — Answer: B. XOR is the "difference detector": $A\oplus B=1$ iff $A\ne B$. Its truth table is $0\oplus0=0,\ 0\oplus1=1,\ 1\oplus0=1,\ 1\oplus1=0$ — true precisely when the two inputs differ, so B is correct (A describes XNOR; C describes OR).

1.3 — Answer: C. Inside an architecture body, every statement (signal assignment, component instantiation, or a process) is a concurrent statement — all execute conceptually in parallel, each re-activating whenever a signal on its sensitivity list changes. The process statement is the one construct that lets you write ordinary top-to-bottom, sequential code — but the process AS A WHOLE is itself one concurrent statement among the others in the architecture. So C; it is what makes sequential-looking code coexist correctly with concurrent hardware description.

1.4 — Answer: C. "Sequential" describes order, not speed or repetition: statements inside a process execute one after another, in the order written, each seeing the effect of the one before it — exactly how software executes. (A) confuses it with "fast"; (B) confuses it with "iterative"/looping.

1.5 — Answer: B. Syntax is the set of rules governing how legal statements are WRITTEN (keywords, punctuation, ordering); semantics is what those statements MEAN once compiled — the behaviour or hardware they imply. So the pair is grammar and meaning. A language can be syntactically valid yet describe the wrong hardware (a semantic error), or vice-versa.

1.6 — Answer: B. Propagation delay $t_{pd}$ is the real, physical delay through combinational logic or a gate: the time between an input changing and the corresponding output settling to its new value. It is unrelated to flip-flop initialization (A) and is not the clock period (C, which is instead bounded below by the sum of propagation delays around the slowest path).

1.7 — Answer: B. A process re-evaluates its body every time a signal in its sensitivity list changes value — those signals must be the process's inputs (anything read inside the process, e.g. in the "combinational" style). Listing an output would be pointless (the process cannot react to its own write) and is a classic simulation-mismatch bug when omitted or over-included.

1.8 — Answer: A. Concurrent statements are event-driven: each one re-executes whenever (is "triggered" by) a change on a signal it reads — there is no fixed top-to-bottom order among them (B, which is the sequential-statement rule) and no requirement that execution wait for a fixed delay (C, delays only model gate timing, they don't define the triggering mechanism).

1.9 — Answer: C. A sequential statement is one legal only inside a process (or subprogram) and executed in program order. Option A pairs two genuine sequential statements (variable assignment; if/then/else) with a concurrent "selected signal assignment" — not sequential. Option B similarly mixes in a "conditional concurrent signal assignment." Only C — (sequential) signal assignment, loop, and variable assignment — lists three statements that are all legitimately sequential.

1.10 — Answer: A. A VHDL variable (local to a process) updates immediately at the point of assignment — the very next statement sees the new value. This is the key contrast with a signal, whose new value is only visible after the current simulation delta-cycle/process suspends (the trap this question is testing).