Question 4 of 6: 3-Bit Synchronous Counter with Count-Enable

Question 4: 3-Bit Synchronous Counter with Count-Enable (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Three positive-edge-triggered JK flip-flops labelled $Q_C$ (MSB), $Q_B$, $Q_A$ (LSB); required state sequence $000\to001\to\cdots\to111\to000\ldots$; part (b) adds a level-sensitive COUNT ENABLE input CTE.

Find. (a) The $J,K$ excitation equations and circuit for the synchronous up-counter; (b) the modification that holds the count when CTE is LOW.

Approach. Read each flip-flop's required toggle condition directly off the binary count sequence (a bit toggles exactly when every less-significant bit is already 1), translate "toggle / hold" into $J=K=1$ / $J=K=0$ per the JK excitation rule, then AND every $J,K$ pair with CTE so CTE$=0$ forces hold on all three flip-flops simultaneously.

1. Part (a) — $Q_A$ (LSB) toggles every clock. In an binary up-count, the LSB flips at every single step ($0\to1\to0\to1\ldots$). The JK excitation table gives $J=1,K=X$ for a $0\to1$ transition and $J=X,K=1$ for $1\to0$ — both consistent with $J=K=1$ (permanent toggle mode): $$J_A=K_A=\boxed{1}$$
2. $Q_B$ toggles only when $Q_A=1$. Checking the 8-row state table, $Q_B$ flips exactly on the transitions out of states 001, 011, 101, 111 — i.e. whenever $Q_A=1$ in the present state — and holds whenever $Q_A=0$. Both the toggle rows ($J{=}1$) and hold rows ($J{=}0$) match $Q_A$ exactly, so: $$J_B=K_B=\boxed{Q_A}$$
3. $Q_C$ toggles only when $Q_A=Q_B=1$ (the carry condition). $Q_C$ flips only leaving states 011 and 111, i.e. only when both lower bits are 1: $$J_C=K_C=\boxed{Q_A\cdot Q_B}$$ This one 2-input AND gate ($Q_A\cdot Q_B$) is the only combinational logic the base counter needs; $Q_A$ drives $J_B/K_B$ directly.
4. Part (b) — gate every $J,K$ with CTE. CTE must force $J=K=0$ (hold) on every flip-flop simultaneously when LOW, and reduce exactly to the part-(a) equations when HIGH — ANDing CTE onto each excitation input does both: $$J_A=K_A=\text{CTE},\qquad J_B=K_B=Q_A\cdot\text{CTE},\qquad J_C=K_C=\boxed{Q_A\cdot Q_B\cdot\text{CTE}}$$ $Q_A\cdot\text{CTE}$ needs one new 2-input AND gate; $Q_A\cdot Q_B\cdot\text{CTE}$ reuses the existing $Q_A\cdot Q_B$ AND gate's output ANDed with CTE in a second gate — two extra AND gates total, and $J_A/K_A$ wire directly to CTE with no gate at all. Because holding sets $J=K=0$ on all three flip-flops together, the count freezes at whatever state it was in and the very next CTE-HIGH edge continues the sequence from that same state (no state is skipped or repeated).