Question 1 of 6: Digital Design and VHDL Concepts

Question 1: Digital Design and VHDL Concepts (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Find. The single best answer, with reasoning, for each of the ten 2-mark sub-questions on digital-logic/HDL terminology and design practice.

1.1 — Answer: B. "Synchronous" describes flip-flops, not gates: all flip-flops share a common clock and change state on the same clock edge. Combinational gates settle at their own propagation delay, not "at the same time" (A), and "all events at the same time" (C) is not a meaningful design property.

1.2 — Answer: C. A tristate driver has exactly three output conditions — logic 0, logic 1, and a disconnected, high-impedance (Hi-Z) third state — which is what lets several drivers share one bus line safely. (A) misreads "tri" as three voltage levels; (B) is not a real distinction.

1.3 — Answer: C. Four flip-flops give $2^4=\boxed{16}$ distinct states ($0000$ through $1111$); 15 (B) is the number of NON-zero states, and 8 (A) is $2^3$, one flip-flop short.

1.4 — Answer: A. A ROM is a fixed lookup table: address in, stored data out, so it directly implements any combinational logic function of its address lines (one word per input combination). It cannot implement a register (B, which needs a clocked storage element) or a read-write memory (C, by definition — "read-only" is right there in the name).

1.5 — Answer: C. Synchronous design confines state changes to clock edges; the flip-flop's asynchronous preset/clear inputs bypass the clock entirely, so accepted synchronous-design practice restricts them to system initialization/reset only — using them for ordinary logic (B) reintroduces asynchronous, clock-independent behaviour the whole discipline exists to avoid.

1.6 — Answer: C. Simulation exercises the HDL model against testbench stimuli and checks the resulting waveforms/values, i.e. it exists to verify the design's functional behaviour against its requirements before committing to hardware. Creating physical circuitry (A) is synthesis/place-and-route; inferring gates and flip-flops from the HDL (B) is synthesis, not simulation.

1.7 — Answer: B. "Concurrent" is the direct opposite of "sequential": occurring at the same time (in parallel), which is exactly how independent architecture-level statements in an HDL execute. (C, "same place") confuses concurrency with physical co-location.

1.8 — Answer: B. A structural architecture describes a design purely as interconnected sub-components, so its primary concurrent statement is component instantiation — placing an instance of a component and mapping its ports to signals. "Component configuration" (A) and "component specification" (C) are not the standard structural VHDL construct.

1.9 — Answer: C. The reserved word others is a catch-all covering whatever elements/values were not explicitly listed — every remaining element of an aggregate/array (A) or every remaining value an object could take in a case/selected-assignment choice list (B). It has nothing to do with statements in a model (C is the false statement, hence the correct answer to a "does NOT mean" question).

1.10 — Answer: A. A process meant to synthesize to flip-flops must be triggered only by the clock (and, if used, an asynchronous reset) — so its sensitivity list is the clock, or the clock and reset. Listing all data inputs (B) is the signature of a COMBINATIONAL (not flip-flop-inferring) process, and would make the synthesized hardware behave like a level-sensitive latch/comb path instead of an edge-triggered register.