Question 4 of 6: 4-Bit Synchronous Counter with Count-Enable

Question 4: 4-Bit Synchronous Counter with Count-Enable (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Four positive-edge-triggered JK flip-flops labelled $Q_3$ (MSB) down to $Q_0$ (LSB); required binary up-count sequence $0000\to0001\to\cdots\to1111\to0000\ldots$; part (b) adds a level-sensitive COUNT ENABLE input CTE.

Find. (a) The $J,K$ excitation equations and circuit for the 4-bit synchronous up-counter; (b) the modification that holds the count when CTE is LOW.

Approach. Read each flip-flop's required toggle condition directly off the binary count sequence (a bit toggles exactly when every less-significant bit is already 1 — the same carry-chain condition as a ripple-carry adder), translate "toggle / hold" into $J{=}K{=}1$ / $J{=}K{=}0$ per the JK excitation rule, then AND every $J,K$ pair with CTE so CTE$=0$ forces hold on all four flip-flops simultaneously.

1. Part (a) — $Q_0$ (LSB) toggles every clock. The LSB of a binary up-count flips at every single step ($0\to1\to0\to1\ldots$), which is the permanent-toggle JK condition: $$J_0=K_0=\boxed{1}$$
2. $Q_1$ toggles only when $Q_0=1$. Checking the 16-row state table, $Q_1$ flips exactly on the transitions out of every state where $Q_0=1$ and holds whenever $Q_0=0$ — both toggle and hold rows match $Q_0$ exactly: $$J_1=K_1=\boxed{Q_0}$$
3. $Q_2$ toggles only when $Q_0=Q_1=1$ (first carry condition), $Q_3$ toggles only when $Q_0=Q_1=Q_2=1$ (second carry condition). These are the standard ripple-carry AND-chain: $$J_2=K_2=\boxed{Q_0\cdot Q_1},\qquad J_3=K_3=\boxed{Q_0\cdot Q_1\cdot Q_2}$$ Two AND gates ($Q_0Q_1$ for stage 2, and that output ANDed again with $Q_2$ for stage 3) are the only combinational logic the base counter needs.
4. Part (b) — gate every $J,K$ with CTE. CTE must force $J=K=0$ (hold) on every flip-flop simultaneously when LOW, and reduce exactly to the part-(a) equations when HIGH — ANDing CTE onto each excitation input does both: $$J_0=K_0=\text{CTE},\quad J_1=K_1=Q_0\cdot\text{CTE},\quad J_2=K_2=Q_0Q_1\cdot\text{CTE},\quad J_3=K_3=\boxed{Q_0Q_1Q_2\cdot\text{CTE}}$$ $Q_0\cdot\text{CTE}$ and $Q_0Q_1\cdot\text{CTE}$ each need one new 2-input AND gate; the existing $Q_0Q_1Q_2$ chain gets a third AND stage with CTE. Because holding sets $J=K=0$ on all four flip-flops together, the count freezes at whatever state it was in, and the very next CTE-HIGH edge continues the sequence from that same state with no state skipped or repeated.