Question 1 of 6: Digital Design and VHDL Concepts

Question 1: Digital Design and VHDL Concepts (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Find. The single best answer, with reasoning, for each of the ten 2-mark sub-questions on digital-design/VHDL terminology.

1.1 — Answer: B. "Synchronous" describes the flip-flops, not the combinational gates: in synchronous design every flip-flop is triggered by the same common clock edge, while the combinational gates between them settle asynchronously at their own propagation delays. (A) is wrong because gates are not clocked at all; (C) overstates the definition — events do not all occur simultaneously, only the flip-flop sampling instants are aligned.

1.2 — Answer: C. A tristate driver adds a third electrical state to the usual logic-0/logic-1 pair: logic 0, logic 1, and high impedance (Hi-Z, effectively disconnected). This lets multiple drivers share one bus line as long as only one is enabled at a time. (A) and (B) invent meanings with no standard basis.

1.3 — Answer: C. Four flip-flops give $2^4=\boxed{16}$ distinct states (0000 through 1111). (A) confuses it with $2^3$; (B) is simply $16-1$, a common off-by-one slip when counting "states after zero" instead of total states.

1.4 — Answer: A. A ROM is a fixed lookup table: each address is permanently wired to a stored output pattern, so it directly implements a combinational logic function (any truth table fits, one row per address). It cannot implement a register (B) or read-write memory (C) because, by definition, a ROM's contents cannot be written during normal operation.

1.5 — Answer: C. Good synchronous design practice restricts the flip-flop's asynchronous preset/clear inputs to system initialization/reset only, never to implement ordinary logic decisions — using them for logic would reintroduce race conditions and timing hazards that synchronous design is meant to eliminate. (A) is too absolute (reset genuinely needs them); (B) is exactly the anti-pattern the rule forbids.

1.6 — Answer: C. Simulation exercises the HDL model against test vectors before any hardware exists, so its purpose is to verify that the design's behaviour matches its functional requirements. Creating ASIC/FPGA circuitry (A) is what synthesis and place-and-route do; inferring gates/flip-flops from HDL (B) is what the synthesis tool's structural mapping does — both are downstream of, and distinct from, simulation.

1.7 — Answer: B. "Concurrent" is the VHDL/hardware term for statements or events that happen at the same time (as physically independent hardware genuinely does), the direct opposite of "sequential." (A) describes the opposite; (C) confuses concurrency (timing) with co-location (space).

1.8 — Answer: B. A structural architecture describes a design purely as interconnected sub-blocks; the concurrent statement that places one of those sub-blocks into the design, wiring its ports to signals, is a component instantiation. "Component configuration" (A) and "component specification" (B-worded distractor C) are not the statement that actually creates an instance in the netlist.

1.9 — Answer: C. The reserved word others is a catch-all used inside an aggregate or a case/with-select choice list to mean every remaining array element or every value not explicitly listed (A and B are both legitimate meanings). It never refers to "all statements in a model" — that is not a construct others participates in at all, which is why C is the one that is NOT a meaning.

1.10 — Answer: A. A process meant to synthesize to edge-triggered flip-flops must be sensitive only to the clock (and an asynchronous reset, if used) — listing every data input (B) or output (C) would make the simulation re-evaluate on data changes between clock edges, which is exactly the semantic mismatch that causes simulation/synthesis mismatches on this class of process.