Question 4 of 6: 4-Bit Synchronous Counter with Count-Enable

Question 4: 4-Bit Synchronous Counter with Count-Enable (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Four positive-edge-triggered JK flip-flops labelled $Q_D$ (MSB), $Q_C$, $Q_B$, $Q_A$ (LSB); required state sequence $0000\to0001\to\cdots\to1111\to0000\ldots$; part (b) adds a level-sensitive COUNT ENABLE input CTE.

Find. (a) The $J,K$ excitation equations and circuit for the 4-bit synchronous up-counter; (b) the modification that holds the count when CTE is LOW.

Approach. Read each flip-flop's toggle condition directly off the binary count sequence (a bit toggles exactly when every less-significant bit is already 1, the ripple-carry condition), translate "toggle / hold" into $J{=}K{=}1$ / $J{=}K{=}0$ per the JK excitation rule, then AND every $J,K$ pair with CTE so CTE$=0$ forces hold on all four flip-flops simultaneously.

1. Part (a) — $Q_A$ (LSB) toggles every clock. The LSB of a binary up-count flips at every step: $$J_A=K_A=\boxed{1}$$
2. $Q_B,Q_C,Q_D$ toggle only when every less-significant bit is already 1 (ripple-carry chain). Checking the 16-row state table, $Q_B$ flips exactly when $Q_A{=}1$; $Q_C$ flips only when $Q_A{=}Q_B{=}1$ (the $0011\to0100$ carry); $Q_D$ flips only when $Q_A{=}Q_B{=}Q_C{=}1$ (the single $0111\to1000$ carry): $$J_B=K_B=Q_A,\qquad J_C=K_C=Q_AQ_B,\qquad J_D=K_D=\boxed{Q_AQ_BQ_C}$$ Three cascaded AND gates ($Q_A{\cdot}Q_B$, then that result $\cdot\,Q_C$) are the only combinational logic the base counter needs.
3. Part (b) — gate every $J,K$ with CTE. ANDing CTE onto each excitation input forces $J{=}K{=}0$ (hold) on all four flip-flops together when CTE is LOW, and reduces exactly to the part-(a) equations when CTE is HIGH: $$J_A=K_A=\text{CTE},\ \ J_B=K_B=Q_A\cdot\text{CTE},\ \ J_C=K_C=Q_AQ_B\cdot\text{CTE},\ \ J_D=K_D=\boxed{Q_AQ_BQ_C\cdot\text{CTE}}$$ This reuses the same $Q_A{\cdot}Q_B$ and $Q_AQ_B{\cdot}Q_C$ AND-gate outputs from part (a), each additionally ANDed with CTE in one more gate (three extra 2-input AND gates total; $J_A/K_A$ wires directly to CTE with no gate). Because holding sets $J{=}K{=}0$ on all four flip-flops at once, the count freezes exactly where it was and the next CTE-HIGH edge continues the sequence from that same state.