Question 4 of 6: 3-Bit Synchronous Counter with Count-Enable

Question 4: 3-Bit Synchronous Counter with Count-Enable (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. Three positive-edge-triggered JK flip-flops labelled $Q_C$ (MSB), $Q_B$, $Q_A$ (LSB); required state sequence $000\to001\to\cdots\to111\to000\ldots$; part (b) adds a level-sensitive COUNT ENABLE input CTE.

Find. (a) The $J,K$ excitation equations and circuit for the 3-bit synchronous up-counter; (b) the modification that holds the count when CTE is LOW.

Approach. Read each flip-flop's required toggle condition directly off the binary count sequence (a bit toggles exactly when every less-significant bit is already 1, the ripple-carry condition), translate "toggle / hold" into $J{=}K{=}1$ / $J{=}K{=}0$ per the JK excitation rule, then AND every $J,K$ pair with CTE so CTE$=0$ forces hold on all three flip-flops simultaneously.

1. Part (a) — $Q_A$ (LSB) toggles every clock. The LSB of a binary up-count flips at every single step ($0\to1\to0\to1\ldots$), the permanent-toggle JK condition: $$J_A=K_A=\boxed{1}$$
2. $Q_B$ toggles only when $Q_A=1$; $Q_C$ toggles only when $Q_A=Q_B=1$. Checking the 8-row state table, $Q_B$ flips exactly on transitions where $Q_A=1$ and holds when $Q_A=0$; $Q_C$ flips only on the single carry condition $Q_A=Q_B=1$ (the $011\to100$ transition): $$J_B=K_B=\boxed{Q_A},\qquad J_C=K_C=\boxed{Q_A\cdot Q_B}$$ One AND gate ($Q_A\cdot Q_B$) is the only combinational logic the base counter needs.
3. Part (b) — gate every $J,K$ with CTE. CTE must force $J=K=0$ (hold) on every flip-flop simultaneously when LOW, and reduce exactly to the part-(a) equations when HIGH — ANDing CTE onto each excitation input does both: $$J_A=K_A=\text{CTE},\quad J_B=K_B=Q_A\cdot\text{CTE},\quad J_C=K_C=\boxed{Q_A Q_B\cdot\text{CTE}}$$ $Q_A\cdot\text{CTE}$ needs one new 2-input AND gate; $Q_A Q_B\cdot\text{CTE}$ reuses the existing $Q_A\cdot Q_B$ AND gate's output ANDed with CTE in a second gate — two extra AND gates total, and $J_A/K_A$ wire directly to CTE with no gate at all. Because holding sets $J=K=0$ on all three flip-flops together, the count freezes at whatever state it was in and the very next CTE-HIGH edge continues the sequence from that same state (no state is skipped or repeated).