Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)
Notes on this paper
17-Comp-A2, Digital Systems Design — National Exams, May 2018. Closed-book, 3 hours; six 20-mark questions, FIVE constitute a complete exam (all six answered below as a complete study resource).
Reference texts: Mano & Ciletti, Digital Design, 6th ed. — VHDL concepts, multiplexer-based realization, Boolean-algebra/K-map minimization, synchronous counter design, and memory/interfacing, covering Questions 1–5; Patterson & Hennessy, Computer Organization and Design, 6th ed. — interrupt-driven I/O, covering Question 6.
Check: the question text specifies "16K x 4" chips, but the figure's own internal chip label reads "16K x 8". The 16K×4 reading is adopted here because it is the only one consistent with each column's data lines being joined together across its two stacked chips: two 16K×4 (nibble-wide) chips stacked in a column combine to a full 16K×8 (byte-wide) bank, exactly matching the six-chip, three-column layout. A column of two chips that were already 8 bits wide individually would have no reason to have their data lines joined at all.
Given. 8-bit CPU, 16-bit address bus $A_{15}$–$A_0$ (64Kbyte $=2^{16}$ space), six 16K×4 memory chips arranged as 3 columns (byte-wide banks) × 2 rows (upper/lower nibble).
Find. (a) the bus-width labels and internal chip wiring; (b) the chip-select decode logic (with Boolean expressions); (c) the address range of each populated chip pair.
Approach. Split the 16-bit address into a low block that addresses within a chip ($2^{14}=16\text{K}$, so 14 lines) and a high block that selects which column/bank is active (the remaining 2 lines); route the low block in parallel to every chip and decode the high block into per-column $\overline{CS}$ signals.
Part (a) — bus widths and chip wiring. Each 16K×4 chip needs $\log_2(16\text{K})=14$ address lines ($A_{13}$–$A_0$, common to all six chips) and 4 data lines. In each column, the TOP chip's 4 data lines wire to the upper nibble $D_7$–$D_4$ of the main data bus and the BOTTOM chip's 4 data lines to the lower nibble $D_3$–$D_0$ — together the pair supplies a full byte. The two high-order address lines $A_{15},A_{14}$ are NOT connected to the chips at all; they instead feed the chip-select decoder in part (b):
$$\text{per-chip address lines}=\boxed{14\ (A_{13}\text{-}A_0)},\qquad \text{per-chip data lines}=4$$
Part (b) — decode $A_{15},A_{14}$ into three chip-selects. With 14 address lines already accounting for $16\text{K}$ addresses per bank, the remaining 2 high-order lines $A_{15},A_{14}$ can address up to 4 banks ($2^2=4$), of which the 3 populated columns use 3:
$$CS_0=\bar A_{15}\bar A_{14},\qquad CS_1=\bar A_{15}A_{14},\qquad CS_2=\boxed{A_{15}\bar A_{14}}$$
Implementation: two inverters generate $\bar A_{15},\bar A_{14}$; three 2-input AND gates produce $CS_0,CS_1,CS_2$ (each then drives, in parallel, BOTH chips — upper-nibble and lower-nibble — of its column, since the pair must be selected/deselected together to keep the byte coherent). The fourth combination, $A_{15}A_{14}=11$ ($CS_3$), is left unconnected — no chip is installed there.
Part (c) — address range per column. Each active $\overline{CS_i}$ spans exactly $16\text{K}=16384$ consecutive addresses, starting at $i\times16384$:
$$\text{Column 0}:\ \boxed{0000_{16}\text{-}3FFF_{16}}\ (0\text{-}16383),\quad\text{Column 1}:\ 4000_{16}\text{-}7FFF_{16}\ (16384\text{-}32767)$$
$$\text{Column 2}:\ \boxed{8000_{16}\text{-}BFFF_{16}}\ (32768\text{-}49151)$$
The remaining $C000_{16}$-$FFFF_{16}$ ($49152$-$65535$, $16\text{K}$) is unpopulated/reserved for future memory expansion — only 6 of the 8 chips a full 4-way decode could support are provided.
Fig. Q5 — three populated 16K×8 byte banks (0x0000-0xBFFF); $A_{13}$-$A_0$ common to all six chips, $A_{15},A_{14}$ decoded into $CS_0,CS_1,CS_2$, each driving its column's top (D7-D4) and bottom (D3-D0) chip together; $A_{15}A_{14}{=}11$ left unconnected (reserved 0xC000-0xFFFF).
