Question 2 of 6

Question 2 (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) 8-bit registers A=0xFE, B=0x10. (b) 32-bit unsigned addition in general. (c) IEEE-754 single precision, three arbitrary floats A, B, C. (d) a 64-element array of 4-byte values starting at 0x1000.

Find. (a) A+B under both interpretations, with the overflow/no-overflow explanation. (b) whether unsigned 32-bit addition is always representable, with a counter-example if not. (c) whether floating-point addition is associative. (d) the storage layout and the address formula for A[i].

Approach. (a) add the raw bit patterns once, then interpret the same result bits two ways and check each interpretation's overflow rule; (b) find the smallest counter-example; (c) reason from finite-precision rounding at each addition step; (d) apply the standard linear array-address formula.

1. Part (a) — unsigned and signed addition of 0xFE + 0x10. The registers hold the same bit pattern regardless of interpretation, so the hardware performs one addition: $$0xFE+0x10 = 11111110_2+00010000_2 = 100001110_2$$ This 9-bit result truncates to 8 bits in the register, giving stored bits $00001110_2=0x0E$. (i) Unsigned: $A=254,\ B=16$, true sum $=270$. Since 270 exceeds the 8-bit unsigned range (0–255), the register instead holds $270\bmod256=\boxed{14}$, with the carry-out bit signalling unsigned overflow — the arithmetically correct answer (270) cannot be represented in 8 bits. (ii) Signed (2's complement): $A=0xFE=-2$, $B=0x10=+16$, true sum $=-2+16=\boxed{14}$. Since $-128\le14\le127$, this fits exactly in 8-bit signed range — no signed overflow occurred. Both interpretations happen to read the same stored bit pattern (0x0E = 14), but the unsigned view suffered overflow (true value 270 was lost) while the signed view did not (true value 14 was preserved exactly) — overflow is a property of the interpretation, not of the bits themselves.
2. Part (b) — can 32-bit unsigned A+B always be represented in 32 bits? No. Unsigned 32-bit values range 0 to $2^{32}-1=4{,}294{,}967{,}295$; if both operands are near the top of that range, their true sum exceeds it. Example: $A=B=0xFFFFFFFF=4{,}294{,}967{,}295$. The true sum is $8{,}589{,}934{,}590$, which needs 33 bits; the 32-bit register can only hold the low 32 bits, $0xFFFFFFFE=4{,}294{,}967{,}294$, with a carry-out flag marking the overflow. Unsigned addition can always overflow the operand width; the flag exists precisely because the sum is not always representable.
3. Part (c) — is floating-point addition associative? No, not in general. IEEE-754 addition rounds the exact mathematical sum to the nearest representable 24-bit (1 implicit + 23 explicit) mantissa after every single operation, and which values get rounded away depends on the order of operations. A classic case: let $A=1.0$, $B=2^{-24}$, $C=2^{-24}$ (values chosen so each is exactly representable, but $A+2^{-24}$ is not, since it would need 25 significant bits to represent exactly). Computing $(B+C)$ first gives $2^{-23}$, which added to $A$ rounds to a representable value strictly greater than $A$ — the small addition survives. Computing $(A+B)$ first rounds straight back to $A$ (since $2^{-24}$ is below $A$'s representable precision at that magnitude), and adding $C$ to that repeats the same rounding — the small terms are lost entirely. The two orders can therefore produce different final results. $(A+B)+C\neq A+(B+C)$ in general, because each addition independently rounds to finite precision and which terms get rounded away depends on grouping order.
4. Part (d) — array storage and address of A[i]. A unidimensional array of 64 32-bit (4-byte) values is stored linearly: element 0 occupies the first 4 bytes at the base address, element 1 the next 4 bytes, and so on, with no gaps (row-major / sequential layout for a 1-D array). The address of element $i$ is $$\text{addr}(A[i])=\text{base}+i\times(\text{element size})=0x1000+4i$$ For example $A[0]=0x1000$, $A[1]=0x1004$, and the last element $A[63]=0x1000+4\times63=\boxed{0x10FC}$.