25-Comp-A3 Computer Architecture, December 2016, Q5

Question 5 (15 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) A chip with 16 address lines ($2^{16}$ addressable rows) and 4 data pins (D3–D0) per row. (b) target: 8-bit-wide memory, 32KB total capacity, built from copies of the chip in (a).

Find. (a) the chip's total storage capacity in bytes. (b) the minimum chip count and wiring to realize the target memory.

Approach. (a) multiply addressable rows by bits per row and convert to bytes. (b) compare the target's address-space depth and data width against one chip's, then combine chips in parallel for width and decide whether the full address range is needed.

Part (a) — single-chip capacity. The 16 address lines address $2^{16}=65536$ distinct rows, each storing 4 bits (D3–D0): $$\text{capacity}=2^{16}\times4\ \text{bits}=262144\ \text{bits}=\frac{262144}{8}=\boxed{32768\ \text{bytes}=32\text{KB}}$$
Part (b) — synthesizing 32KB, 8-bit-wide from these chips. The target needs $32\text{KB}/1\text{byte}=32768$ addressable 8-bit words, i.e. $\log_2(32768)=15$ address bits (A0–A14). Each chip is only 4 bits wide, so two chips must be placed in parallel to form one 8-bit-wide word: one chip supplies bits D7–D4, the other D3–D0, both driven by the same 15 address lines and the same R/W' and E control lines. Notably, each individual chip already has 16 address lines (addressing $65536$ rows internally) — more than the 32768 words the target needs — so only 15 of each chip's 16 address inputs (A0–A14) are actually connected to the shared address bus; the 16th line (A15) is tied to a fixed logic 0 on both chips, permanently selecting only the lower half of each chip's internal array (the upper half goes unused). Exactly 2 chips are needed (not 4): one per nibble, sharing A0–A14/R-W'/E, each with its unused A15 pin grounded.

Final results — Question 5
Part	Result
(a)	$\boxed{32768}$ bytes $=32$KB
(b)	$\boxed{2}$ chips in parallel (one per nibble), sharing A0–A14/R-W'/E; A15 on each chip tied to 0

Topic: Memory-chip capacity accounting and synthesizing a target memory organization (width $\times$ depth) from narrower building-block chips.

Key relations: chip capacity (bits) $=2^{\text{\#address lines}}\times\text{data width}$; to widen data, place chips in parallel sharing every address/control line, each contributing a disjoint slice of the output word; to shrink usable depth below a chip's native range, tie off the high-order unused address line(s) rather than adding decode logic.

Why this works: address lines and data lines are independent resources — parallel chips sharing an address bus each see the identical row select, so their outputs concatenate into a wider word for free, while a chip's internal depth is fixed by its own address-pin count and is only reduced by not driving every address pin from the system's live address bus.

Common pitfall: assuming 4 chips are needed (2 for width $\times$ 2 for depth) without noticing the given chip's native depth (65536) already exceeds the required depth (32768), so no depth-multiplication chips are needed at all — only width-multiplication.

Source: Patterson & Hennessy, Computer Organization and Design, 6th ed., Ch.5 (memory technology, chip organization); Mano & Ciletti, Digital Design, 6th ed., Ch.7 (memory devices, address decoding).

Question 5 of 6

Question 5 (15 marks)