Question 1 of 6

Question 1 (15 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) a pipelined datapath, optionally 2-way superscalar. (b) 40 instructions (32-bit encoding each), 10 memory-read and 1 memory-write instructions, each memory access moving 4 bytes. (c) the 32-bit word 0x0000FFAB at address 0x10001004.

Find. (a) definitions of structural/data hazards and whether superscalar issue worsens data hazards; (b) minimum bytes read from memory over the 40-instruction run; (c) whether the stored word can be an instruction, data, or either.

Approach. (a) reason from resource contention vs. operand dependence, then from issue width; (b) separate instruction-fetch traffic from data-read traffic and sum only the reads; (c) recall that a von Neumann machine stores instructions and data in the same address space with no tag bits.

1. Part (a) — structural vs. data hazards, and superscalar issue. A structural hazard occurs when two instructions in the pipeline simultaneously need the same hardware resource (a single memory port, a single ALU, a single register-file write port) and the hardware cannot serve both in the same cycle — e.g. a Harvard-style single unified memory port being needed by an instruction fetch and a data load in the same cycle. A data hazard occurs when an instruction needs an operand that is still being produced by an earlier instruction in the pipeline (RAW), or when instruction ordering for writes/reads of the same register would be violated if instructions completed out of their fetch order (WAR, WAW). Yes — a 2-way superscalar pipeline encounters more data hazards than a single-issue pipeline of the same depth, for two compounding reasons: first, fetching/issuing two instructions per cycle instead of one means that a genuine RAW dependence between a producer and a nearby consumer, which single-issue code would naturally have separated by more cycles, is now separated by fewer cycles for the same instruction-count gap (twice as many instructions are in flight per unit time, so the same static distance in the code maps to less slack); second, superscalar issue introduces an entirely new hazard class that cannot occur in a single-issue machine at all — an intra-bundle hazard, where the second of the two instructions issued in the very same cycle depends on the result of the first, and that result is not yet available anywhere in the pipeline to forward. Yes: a 2-way superscalar pipeline sees strictly more data hazards, both because dependent instructions are issued closer together in time and because same-cycle (intra-bundle) RAW hazards are a hazard class single-issue pipelines cannot have.
2. Part (b) — minimum bytes read from memory. Every one of the 40 instructions must be fetched from memory regardless of what it does, at 32 bits (4 bytes) each: $$\text{fetch bytes}=40\times4=160\ \text{bytes}$$ Only the 10 memory-read instructions pull additional data from memory (4 bytes each); the 1 memory-write instruction sends data to memory and does not read data from it, so it adds nothing to this count: $$\text{data-read bytes}=10\times4=40\ \text{bytes}$$ $$\boxed{\text{minimum bytes read}=160+40=200\ \text{bytes}}$$
3. Part (c) — instruction, data, or either? Nothing in the 32-bit pattern 0x0000FFAB itself carries a tag saying "I am an instruction" or "I am data" — a von Neumann machine stores both in the same physical memory using the same addressing, so any bit pattern is simultaneously a syntactically valid potential instruction encoding (whether it decodes to something the ISA defines depends on the specific instruction-format field layout, but some interpretation almost always exists) and an equally valid data value (e.g. the unsigned integer 65,451, a packed bit-field, part of a string). What actually determines the role of this particular word is the access path that reaches address 0x10001004: if the processor arrives there via the program counter during instruction fetch, the word is being used as an instruction; if a load/store instruction computes this address as an operand address, the same bits are being used as data. Either — the bit pattern is equally valid as an instruction or as data; only whether the processor reached this address via PC-fetch or via a load/store address tells you which role it is playing.