25-Comp-A3 Computer Architecture, December 2017, Q5

Question 5 (15 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) a memory chip: 15 address lines (A0–A14), 2 bidirectional data pins (D1, D0), a chip-enable E, a read/write control. (b) target: 8-bit-wide, 32KB-total memory built from copies of this chip.

Find. (a) the chip's total capacity in bytes. (b) how many chips (and what wiring) synthesizes the target memory.

Approach. (a) count addressable rows from the address-line count, multiply by the data-pin width to get total bits, convert to bytes. (b) split the requirement into a width-expansion factor (target width / chip width) and a depth-expansion factor (target rows / chip rows), then combine.

Part (a) — chip capacity. 15 address lines (A0–A14) select one of $2^{15}=32{,}768$ distinct rows. Each row exposes exactly 2 data pins (D1, D0), i.e. each addressable row holds 2 bits: $$\text{total bits} = 32{,}768\times2 = 65{,}536\ \text{bits}$$ $$\boxed{\text{total capacity} = 65{,}536/8 = 8{,}192\ \text{bytes} = 8\text{KB}}$$
Part (b) — synthesizing an 8-bit-wide, 32KB memory. Two independent expansions are needed: width (the target needs 8 data bits per address, this chip only offers 2) and depth (the target needs enough distinct addresses to reach 32KB total).
Width expansion: place chips side by side, all sharing the same 15 address lines (A0–A14), the same E, and the same R/W! signal, with each chip contributing 2 of the 8 output bits (chip 0 → D[1:0], chip 1 → D[3:2], chip 2 → D[5:4], chip 3 → D[7:6]): $$\text{width chips}=8/2=4$$ Depth expansion: the target needs $32\text{KB}=32{,}768$ distinct byte addresses. A single chip already provides exactly $2^{15}=32{,}768$ rows — precisely matching the target depth — so no depth expansion is required: one row of 4 width-expansion chips already spans the full 32,768-address range with no additional address decoding logic. $$\boxed{\text{total chips required} = 4\ (\text{width})\times1\ (\text{depth}) = 4}$$ Wiring: tie all 15 address lines (A0–A14) in parallel across all 4 chips, tie E and R/W! together across all 4 chips (a single global enable/read-write control, since there is only one depth group so no address-decoded chip-select logic is needed at all), and concatenate each chip's 2-bit D1:D0 output into its own 2-bit slice of the 8-bit system data bus.

Final results — Question 5
Part	Result
(a)	$\boxed{8{,}192}$ bytes (32,768 rows × 2 bits)
(b)	$\boxed{4}$ chips (4-way width expansion, no depth expansion; shared address/enable/R-W, D-pins concatenated)

Topic: Memory-chip capacity from pin count, and width- vs. depth-expansion when composing chips into a larger memory.

Key relations: rows $=2^{\#\text{address lines}}$; capacity (bits) $=$ rows $\times$ data width; width chips $=$ target width / chip width; depth groups $=\lceil$target rows / chip rows$\rceil$; total chips $=$ width chips $\times$ depth groups.

Why this works: width and depth are orthogonal axes of memory composition — wiring chips side-by-side (sharing address/control, concatenating data) widens the word without adding capacity per address, while wiring chips as separate address-decoded groups (sharing data bus, splitting the address range with extra decode logic on the high address bits) adds capacity without widening the word. Here the chip's own row count happens to exactly equal the target's address-space size, which is why depth expansion collapses to a single group with zero extra decode logic — a coincidence of the numbers, not a general rule.

Common pitfall: reflexively adding chip-select decode logic even when a single depth group already covers the full target address range; multiplying width chips by depth groups in the wrong order, or forgetting that depth expansion (unlike width expansion) requires an address decoder on the extra high-order address bits.

Source: Patterson & Hennessy, Computer Organization and Design, 6th ed., Ch.5 (memory technology, chip organization, width/depth expansion).

Question 5 of 6

Question 5 (15 marks)