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25-Comp-A3 Computer Architecture: May 2017

Nivaar worked solution (AI-drafted; not reviewed by a licensed engineer)

  1. Question 1 Two's-Complement Addition, IEEE-754 Multiply Precision, and Byte-Addressable Array Layout
  2. Question 2 Opcode Space and Register-Field Width in a Fixed 32-bit Instruction Encoding
  3. Question 3 Minimum Memory Traffic for Program Execution, and Polling vs. Interrupt-Driven I/O
  4. Question 4 Set-Associative Cache Indexing, Address Decoding, and Registers vs. Caches
  5. Question 5 Memory-Chip Capacity, Composing a Wider/Deeper Memory, and Byte-Interleaved Chip Selection
  6. Question 6 Multi-Cycle CPI Trade-off Between Clock Speed and Instruction Cost, and the Rise of Caches in the x86 Family

Start with Question 1 →

98-Comp-A3, Computer Architecture — National Exams, May 2017. Open-book, 3 hours; six questions of equal value (20 marks each); FIVE constitute a complete exam (all six answered below as a complete study resource).

Reference texts: Patterson & Hennessy, Computer Organization and Design, 6th ed. — number representation and IEEE-754 floating point (Q1a–b), memory addressing and array layout (Q1c–d), instruction encoding and RISC field allocation (Q2), memory-system performance (Q3a), programmed vs. interrupt-driven I/O (Q3b), cache organization and set-associative indexing (Q4), memory-chip capacity and composition (Q5), and multi-cycle datapath performance and cache history (Q6).