Question 6 of 6: Multi-Cycle CPI Trade-off Between Clock Speed and Instruction Cost, and the Rise of Caches in the x86 Family

Question 6: Multi-Cycle CPI Trade-off Between Clock Speed and Instruction Cost, and the Rise of Caches in the x86 Family (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) Original implementation cycle counts: LI 5, ARITH/BRANCH 6, MEM READ 7, MEM STORE 5; modified implementation: identical except LI 6, with clock frequency $+5\%$. Instruction mix: LI 15%, ARITH 45%, MEM READ 20%, MEM STORE 10%, BRANCH 10%. (b) The historical fact that early x86 chips had no cache and later ones did.

Find. (a) Which implementation executes the given instruction mix faster, and by what factor/percentage. (b) The purpose of caches, and why they appeared only in later x86 generations.

Approach. (a) compute the average CPI for each implementation by weighting each instruction's cycle count by its frequency, then convert to average time-per-instruction using each implementation's own clock period (the modified one is $1/1.05$ times the original), and compare. (b) reason about the CPU–memory speed gap over time and the cost of on-chip cache real estate.

1. Part (a) — original vs. modified implementation. Average CPI (cycles per instruction) for the ORIGINAL implementation, weighting each instruction class by its frequency: $$\text{CPI}_{\text{orig}} = 0.15(5)+0.45(6)+0.10(6)+0.20(7)+0.10(5) = 0.75+2.70+0.60+1.40+0.50 = \boxed{5.95\text{ cycles/instr}}$$ For the MODIFIED implementation, only LI changes (5$\to$6 cycles), all else identical: $$\text{CPI}_{\text{mod}} = 0.15(6)+0.45(6)+0.10(6)+0.20(7)+0.10(5) = 0.90+2.70+0.60+1.40+0.50 = \boxed{6.10\text{ cycles/instr}}$$ Let $T$ be the original clock period; the modified clock runs 5% faster, so its period is $T/1.05$. Average time per instruction is CPI $\times$ clock period: $$t_{\text{orig}} = 5.95\,T \qquad t_{\text{mod}} = 6.10\times\frac{T}{1.05} = 5.8095\,T$$ Since $5.8095\,T < 5.95\,T$, the MODIFIED implementation executes the average instruction faster, by a factor of $$\frac{t_{\text{orig}}}{t_{\text{mod}}} = \frac{5.95}{5.8095} = \boxed{1.0242\times}\quad\Rightarrow\quad\text{modified is }\boxed{2.42\%}\text{ faster}$$ Even though the modified machine needs MORE cycles for every instruction class it changed (LI) and has a HIGHER average CPI overall (6.10 > 5.95), its 5% shorter clock period more than compensates because LI is a minority (15%) of the mix — illustrating that CPI alone never determines performance; only CPI $\times$ clock period (equivalently, CPI $/$ clock frequency) does.
2. Part (b) — why caches appeared only in later x86 generations. Caches exist to bridge the gap between CPU cycle time and (much slower) main-memory (DRAM) access time: by keeping recently/nearby-used instructions and data in small, fast on-chip storage, a cache lets the CPU avoid a full DRAM-speed access on most memory references, which is essential once the CPU can execute many instructions in the time a single DRAM access takes. The EARLIEST x86 generations (the 8086/8088 and 80186) ran at low clock frequencies that were much closer to contemporary DRAM speeds — the CPU-memory speed GAP was small, so a memory access cost only a few CPU cycles and a cache bought little benefit relative to its cost. On-chip cache also consumes substantial transistor budget and die area, which was scarce and expensive on the process technology of the early 1980s; simpler, cache-less designs were the economical choice. By the time of the 80286 (mid-80s) and especially the 80386/486, CPU clock frequencies had risen much faster than DRAM access times had fallen (DRAM speed improvements lagged CPU speed improvements for decades — the "memory wall"), so a memory access now cost many CPU cycles; simultaneously, transistor budgets (Moore's Law) had grown enough to afford dedicating die area to an on-chip cache. Caches exist to hide the CPU–memory speed gap; early x86 chips skipped them because that gap was still small and die area was too precious, while later generations both NEEDED a cache (the gap had widened) and could AFFORD one (more transistors available).