Memory-Chip Capacity, Composing a Wider/Deeper Memory, and Byte-Interleaved Chip Selection: 25-Comp-A3 Computer Architecture, May 2017, Q5

Question 5: Memory-Chip Capacity, Composing a Wider/Deeper Memory, and Byte-Interleaved Chip Selection (20 marks)

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Given. (a) A memory chip: 16 address lines A0–A15, one $R/\overline{W}$ line, one enable E, and 4 bidirectional data pins D3–D0 (high-Z when E=0). (b) The chip from (a); target: an 8-bit-wide, 128KB memory. (c) A 32-bit system bus (L0–L31, ME, $R/\overline{W}$, D0–D7); target: two 1KB, 8-bit-wide chips (styled per (b)) occupying the byte-interleaved 2KB range 0xF0000000–0xF00007FF.

Find. (a) The chip's total capacity in bytes. (b) The minimum number of chips, and how to connect them, to realize an 8-bit-wide 128KB memory. (c) The address-decode and interleave logic connecting two 1KB chips to the given system bus.

Approach. (a) capacity $=$ (number of addressable rows) $\times$ (bits per row). (b) reaching a target width means placing chips side by side (each contributing its own data-bit slice); reaching a target depth beyond one chip's own address range means stacking groups and using an extra address bit, through a decoder, to enable only the active group. (c) byte-interleaving splits the address space between chips by its LOWEST address bit, so that bit becomes a chip-select input rather than part of either chip's own address.

Part (a) — chip capacity. 16 address lines address $2^{16}=65536$ distinct rows, and each row is 4 bits wide (D3–D0): $$\text{capacity} = 2^{16}\times4\text{ bits} = 262144\text{ bits} = \frac{262144}{8}\text{ bytes} = \boxed{32768\text{ bytes} = 32\text{KB}}$$
Part (b) — an 8-bit-wide 128KB memory from 32KB×4-bit chips. Width: each chip supplies only 4 of the needed 8 data bits, so two chips placed side by side (sharing all 16 address lines and both control signals, one chip's D3–D0 feeding system bits 7–4, the other's feeding bits 3–0) give an 8-bit-wide, $65536$-location, $65536\times1\text{ byte}=64\text{KB}$ module. Depth: $128\text{KB}/64\text{KB}=2$, so two such 64KB modules (4 chips total) must be stacked to reach 128KB, using one extra address line (call it A16, the next bit above the 16 the chips already use) to pick which module is active: A16 feeds a 1-to-2 decoder (or simply A16 and its inverse $\overline{\text{A16}}$) whose two outputs each AND with the system chip-select to drive one module's pair of E inputs, so exactly one module is enabled for any given address. $$\text{total chips} = \underbrace{2}_{\text{width: 4-bit}\to\text{8-bit}}\times\underbrace{2}_{\text{depth: 64KB}\to\text{128KB}} = \boxed{4\text{ chips}}$$ All four chips share A0–A15 and $R/\overline{W}$; each chip's E is (system-select) AND (A16 or $\overline{\text{A16}}$, matching its module); within a module the two chips' D3–D0 buses connect to disjoint halves of the 8-bit data bus.
Part (c) — connecting two 1KB chips, byte-interleaved, to the system bus. Each 1KB (8-bit-wide, per part (b)'s chip style) chip holds $1024$ byte locations, needing $\log_2(1024)=10$ internal address lines. Because addresses are interleaved by the LOWEST bit (even byte $\to$ chip 0, odd byte $\to$ chip 1), that bit, L0, is removed from each chip's own address and used instead as the chip-select input; the NEXT 10 bits, L1–L10, supply each chip's 10 internal address lines (both chips see the SAME L1–L10, since together they must span $2\times1024=2048$ interleaved bytes $=2$KB). The remaining upper bits, L11–L31, must match the fixed pattern of the base address $0\text{xF0000000}$ (whose bits above bit 11 are all fixed for the whole 2KB window) — a comparator (a wide AND gate fed by each address bit, inverted where the base-address bit is 0) produces a single MATCH signal, which is ANDed with ME to form the module's overall select.

Fig. Q5(c) — address decode for two byte-interleaved 1KB chips: L1–L10 feed both chips' internal address lines (A0–A9), L11–L31 are compared to the fixed base 0xF0000000 to form MATCH, and L0 (direct/inverted) combines with MATCH·ME to enable exactly one chip per access. D0–D7 and $R/\overline{W}$ connect in parallel to both chips (only the enabled chip drives/latches).

Summarizing the connections: L1–L10 $\to$ both chips' A0–A9 (identical, since interleaving only removes the LSB); L11–L31 $\to$ a comparator against the fixed high bits of 0xF0000000, producing MATCH; chip 0's E $=$ ME $\cdot$ MATCH $\cdot\overline{\text{L0}}$ (even addresses); chip 1's E $=$ ME $\cdot$ MATCH $\cdot$ L0 (odd addresses); D0–D7 and $R/\overline{W}$ connect identically, in parallel, to both chips — no bus contention arises because E is mutually exclusive between the two chips for any single address.

Final results — Question 5
Part	Result
(a) chip capacity	$\boxed{32768\text{ bytes (32KB)}}$
(b) chips needed for 8-bit×128KB	$\boxed{4}$ chips (2 wide $\times$ 2 deep), extra address bit A16 selects the active pair
(c) internal address lines per 1KB chip	10 (L1–L10)
(c) chip-select logic	E$_0$ = ME·MATCH·$\overline{\text{L0}}$; E$_1$ = ME·MATCH·L0; MATCH = (L11–L31 = base pattern)

Topic: Memory-chip capacity accounting, composing width/depth from smaller chips, and address decoding with byte-interleaved chip selection.

Key relations: chip capacity $=2^{\#\text{address lines}}\times(\text{data-pin width})$; achieving a target width needs (target width / chip width) chips in parallel; achieving a target depth beyond one chip's range needs (target depth / achieved-width depth) groups, selected by extra high-order address bits through a decoder; byte-interleaving removes the LOW-order address bit(s) from each chip's own addressing and reassigns them as a chip-select.

Why this works: a memory chip's data pins and address pins are independent resources — adding chips side by side widens the data bus without changing how many locations exist, while adding chips "behind" a decoder deepens the address space without changing the data width; interleaving by the low bit rather than a high bit is what makes CONSECUTIVE addresses land on alternating chips, enabling wide, low-latency burst-style access.

Common pitfall: interleaving by a high address bit instead of the low bit (which would put entire halves of the address range on each chip rather than alternating bytes); forgetting that only ONE extra address bit (not a full new address field) is needed to double capacity via depth-stacking, since the existing 16 address lines are reused unchanged for both stacked groups; allowing both chips to drive D0–D7 simultaneously (bus contention) by forgetting the E signals must be mutually exclusive.

Source: Patterson & Hennessy, Computer Organization and Design, 6th ed., Ch.5 (memory technology, chip organization, address decoding).

Question 5 of 6: Memory-Chip Capacity, Composing a Wider/Deeper Memory, and Byte-Interleaved Chip Selection

Question 5: Memory-Chip Capacity, Composing a Wider/Deeper Memory, and Byte-Interleaved Chip Selection (20 marks)