Lead/lag controller design in the frequency domain: 22-Elec-A2 Systems and Control, December 2014, Q6

Question 6 — Lead/lag controller design in the frequency domain [8 + 12]

Question text not reproduced: the examination questions are © Engineers and Geoscientists BC. Open the official past paper (linked at the top of this page) to read the question, then follow the worked solution below.

Figure-read values. Figure Q6.1 is a printed Bode plot with blank answer boxes; the margins and error constants below are read off the curves. Representative reads consistent with the plotted shapes (compensated crossover pushed to higher frequency with a phase “hump”) are used throughout and flagged as reads.

Given. Type 1 loop; target $K_v=1/e_{ss(ramp)}=10$; $PO\lt20\%\Rightarrow\zeta\gtrsim0.46$, design for $\zeta\approx0.55$ ($\text{PM}\approx55^\circ$).

Find. Controller type, the two sets of margins/specs, and $G_c(s)$.

Part A — Read-off and specifications [8]

Lead or lag? The compensated curve crosses 0 dB at a higher frequency ($\approx4$ rad/s vs $\approx1$) and carries a positive phase bump — a $\boxed{\textbf{LEAD controller}}$ (a lag controller would lower the crossover).
Uncompensated reads. $\Phi_{mu}\approx30^\circ$, $\omega_{cu}\approx1$ rad/s, $K_{vu}\approx3$. Then $e_{ss(ramp)}=1/3=0.33$ (fails), $\zeta\approx\Phi_{mu}/100=0.30\Rightarrow PO\approx37\%$ (fails), $T_{settle}\approx\dfrac{4}{\zeta\omega_{cu}}\approx13$ s.
Compensated reads. $\Phi_{mc}\approx55^\circ$, $\omega_{cc}\approx4$ rad/s, $K_{vc}\approx10$. Then $e_{ss(ramp)}=0.1$ (meets), $\zeta\approx0.55\Rightarrow PO\approx12.6\%$ (meets), $T_{settle}\approx\dfrac{4}{0.55(4)}\approx1.8$ s.

Uncompensated (blue) vs compensated (green): the lead lifts the crossover and phase, restoring margin while raising $K_v$ to 10.

Part B — Lead-controller design [12]

Approach. Set the DC gain for $K_v=10$, choose $\alpha$ for the required phase lead, then place the lead’s maximum phase at the new crossover.

DC gain for $K_v$. $G_c(0)=a_0$ scales the Type-1 velocity constant: $a_0=\dfrac{K_{vc}}{K_{vu}}=\dfrac{10}{3}=\boxed{3.33}$.
Lead ratio. For a peak lead of $\phi_m\approx40^\circ$, $\alpha=\dfrac{1-\sin\phi_m}{1+\sin\phi_m}=0.217$.
Time constant. Put the lead peak at $\omega_m=\omega_{cc}=4$ rad/s: $T=\dfrac{1}{\omega_m\sqrt{\alpha}}=0.536$ s, so the zero is at $1/T=1.87$ and the pole at $1/(\alpha T)=8.58$.
Assemble. With $a_1=a_0T=1.79$ and $b_1=\alpha T=0.116$, $$\boxed{G_c(s)=\frac{1.79\,s+3.33}{0.116\,s+1}}\;=\;3.33\,\frac{s+1.87}{s+8.58}\cdot\frac{8.58}{1.87}.$$ DC gain $3.33$ (sets $K_v=10$), high-frequency gain $a_1/b_1=15.4$ (the lead boost).

Quantity	Uncompensated	Compensated
$\Phi_m$	$\approx30^\circ$	$\approx55^\circ$
$\omega_c$ (rad/s)	$\approx1$	$\approx4$
$K_v$ / $e_{ss(ramp)}$	$3$ / $0.33$	$10$ / $0.10$
$PO$	$\approx37\%$	$\approx12.6\%$
Controller	$G_c(s)=\dfrac{1.79s+3.33}{0.116s+1}$ (lead)

Lead compensator pole–zero: zero $-1.87$ inside, pole $-8.58$ outside.

Question 6 of 8: Lead/lag controller design in the frequency domain

Question 6 — Lead/lag controller design in the frequency domain [8 + 12]

Part A — Read-off and specifications [8]

Part B — Lead-controller design [12]